參數(shù)資料
型號(hào)： AD5734RBREZ
廠商： Analog Devices Inc
文件頁數(shù)： 22/32頁
文件大?。?/td> 0K
描述： IC DAC 14BIT DSP/SRL 24TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Software Configurable 14-Bit Quad-Channel Unipolar/Bipolar Voltage Output Using AD5734R (CN0084)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 10µs
位數(shù)： 14
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 雙 ±
功率耗散（最大）： 310mW
工作溫度： -40°C ~ 80°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm）裸露焊盤
供應(yīng)商設(shè)備封裝： 24-TSSOP 裸露焊盤
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 100k
產(chǎn)品目錄頁面： 784 (CN2011-ZH PDF)
AD5724R/AD5734R/AD5754R
Rev. E | Page 29 of 32
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the
power and thermal status of the AD5724R/AD5734R/AD5754R. The power control register options are shown in Table 27 and Table 28.
Table 27. Programming the Power Control Register
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
X
OCD
OCC
OCB
OCA
0
TSD
PUREF
PUD
PUC
PUB
PUA
Table 28. Power Control Register Functions
Option
Description
PUA
DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). After setting this bit to power DAC A, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC A powers down automatically on detection of an overcurrent, and PUA is cleared to reflect this.
PUB
DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). After setting this bit to power DAC B, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register
is cleared, DAC B powers down automatically on detection of an overcurrent, and PUB is cleared to reflect this.
PUC
DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down
mode (default). After setting this bit to power DAC C, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register
is cleared, DAC C powers down automatically on detection of an overcurrent, and PUC is cleared to reflect this.
PUD
DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down
mode (default). After setting this bit to power DAC D, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register
is cleared, DAC D powers down automatically on detection of an overcurrent, and PUD is cleared to reflect this.
PUREF
Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the
internal reference in power-down mode (default).
TSD
Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this
bit is set.
OCA
DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set.
OCB
DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set.
OCC
DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set.
OCD
DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set.
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