參數(shù)資料
型號(hào): AD573JD
廠(chǎng)商: ANALOG DEVICES INC
元件分類(lèi): ADC
英文描述: RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 15V; Output Voltage (Vdc): 24V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85%
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP20
封裝: HERMETIC SEALED, CERAMIC, DIP-20
文件頁(yè)數(shù): 8/8頁(yè)
文件大?。?/td> 327K
代理商: AD573JD
AD573
REV. A
–8–
C841–9–5/84
PRINTED
IN
U.S.A.
It is also possible to write a faster-executing assembly-language
routine to control the AD573. Such a routine will require a de-
lay between starting and reading the converter. This can be eas-
ily implemented by calling the Apple’s WAIT subroutine (which
resides at location $FCA8) after loading the accumulator with a
number greater than or equal to two.
8085-Series Microprocessor Interface
The AD573 can also be used with 8085-series microprocessors.
These processors use separate control signals for RD and WR,
as opposed to the single R/W control signal used in the 6800/
6500 series processors.
There are two constraints related to operation of the AD573
with 8085-series processors. The first problem is the width of
the CONVERT pulse. The circuit shown in Figure 17 (essen-
tially the same as that shown in Figure 13) will produce a wide
enough CONVERT pulse when the 8085 is running at 5 MHz.
For 8085 systems running at slower clock rates (3 MHz), the
flip-flop-based circuit can be eliminated since the WR pulse will
be approximately 500 ns wide.
The other consideration is the access time of the AD573’s three-
state output data buffers, which is 250 ns maximum. It may be
necessary to insert wait states during RD operations from the
AD573. This will not be a problem in systems using memories
with comparable access times, since wait states will have already
been provided in the basic system design.
Figure 17. AD573–8085A Interface Connections
The following assembly-language subroutine can be used to
control an AD573 residing at memory locations 3000H and
3001H. The 10 bits of data are returned (left-justified) in the
DE register pair.
ADC:
LXI H, 3000 ; LOAD HL WITH AD573 ADDRESS
MOV M, A
; START CONVERSION
MVI B, 06
; LOAD DELAY PERIOD
LOOP: DCR B
; DELAY LOOP
JNZ LOOP
;
MOV A, M
; READ LOW BYTE
ANI C0
; MASK LOWER 6 BITS
MOV E, A
; STORE CLEAN LOW BYTE IN E
INR L
; LOAD HIGH BYTE ADDRESS
MOV D, M
; MOVE HIGH BYTE TO D
RET
; EXIT
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Ceramic DIP Package (“D”)
20-Pin Plastic DIP Package (“N”)
P-20A PLCC
相關(guān)PDF資料
PDF描述
AD573JP 10-Bit A/D Converter
AD573KD 10-Bit A/D Converter
AD573KN 10-Bit A/D Converter
AD573KP RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 15V; Output Voltage (Vdc): 3.3V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85%
AD573SD 10-Bit A/D Converter
相關(guān)代理商/技術(shù)參數(shù)
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