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參數(shù)資料
| 型號： | AD573JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit A/D Converter |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 327K |
| 代理商： | AD573JP |
AD573
REV. A
–8–
C841–9–5/84
PRINTED
IN
U.S.A.
It is also possible to write a faster-executing assembly-language
routine to control the AD573. Such a routine will require a de-
lay between starting and reading the converter. This can be eas-
ily implemented by calling the Apple’s WAIT subroutine (which
resides at location $FCA8) after loading the accumulator with a
number greater than or equal to two.
8085-Series Microprocessor Interface
The AD573 can also be used with 8085-series microprocessors.
These processors use separate control signals for RD and WR,
as opposed to the single R/W control signal used in the 6800/
6500 series processors.
There are two constraints related to operation of the AD573
with 8085-series processors. The first problem is the width of
the CONVERT pulse. The circuit shown in Figure 17 (essen-
tially the same as that shown in Figure 13) will produce a wide
enough CONVERT pulse when the 8085 is running at 5 MHz.
For 8085 systems running at slower clock rates (3 MHz), the
flip-flop-based circuit can be eliminated since the WR pulse will
be approximately 500 ns wide.
The other consideration is the access time of the AD573’s three-
state output data buffers, which is 250 ns maximum. It may be
necessary to insert wait states during RD operations from the
AD573. This will not be a problem in systems using memories
with comparable access times, since wait states will have already
been provided in the basic system design.
Figure 17. AD573–8085A Interface Connections
The following assembly-language subroutine can be used to
control an AD573 residing at memory locations 3000H and
3001H. The 10 bits of data are returned (left-justified) in the
DE register pair.
ADC:
LXI H, 3000 ; LOAD HL WITH AD573 ADDRESS
MOV M, A
; START CONVERSION
MVI B, 06
; LOAD DELAY PERIOD
LOOP: DCR B
; DELAY LOOP
JNZ LOOP
;
MOV A, M
; READ LOW BYTE
ANI C0
; MASK LOWER 6 BITS
MOV E, A
; STORE CLEAN LOW BYTE IN E
INR L
; LOAD HIGH BYTE ADDRESS
MOV D, M
; MOVE HIGH BYTE TO D
RET
; EXIT
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Ceramic DIP Package (“D”)
20-Pin Plastic DIP Package (“N”)
P-20A PLCC
相關PDF資料 |
PDF描述 |
|---|---|
| AD573KD | 10-Bit A/D Converter |
| AD573KN | 10-Bit A/D Converter |
| AD573KP | RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 15V; Output Voltage (Vdc): 3.3V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85% |
| AD573SD | 10-Bit A/D Converter |
| AD574 | Complete 12-Bit A/D Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD573JPZ | 功能描述:IC ADC 10BIT SAR REGISTER 20PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD573KD | 功能描述:IC ADC 10BIT SAR REG 20-CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD573KD/+ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD573KN | 制造商:Analog Devices 功能描述:ADC Single SAR 10-bit Parallel 20-Pin PDIP N 制造商:Rochester Electronics LLC 功能描述:IC, MONO 10-BIT A/D CONV - Bulk |
| AD573KN/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
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