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參數(shù)資料
| 型號： | AD574AKP-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/REF/CLK 28-PLCC |
| 標準包裝： | 750 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 28.6k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 725mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極 |
AD574A
REV. B
–9–
Figure 7 shows a complete timing diagram for the AD574A con-
vert start operation. R/C should be low before both CE and CS
are asserted; if R/C is high, a read operation will momentarily
occur, possibly resulting in system bus contention. Either CE or
CS
may be used to initiate a conversion; however, use of CE is
recommended since it includes one less propagation delay than
CS
and is the faster input. In Figure 7, CE is used to initiate the
conversion.
Figure 7. Convert Start Timing
Once a conversion is started and the STS line goes high, convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers cannot be enabled during
conversion.
Figure 8 shows the timing for data read operations. During data
read operations, access time is measured from the point where
CE and R/C both are high (assuming CS is already low). If CS
is used to enable the device, access time is extended by 100 ns.
Figure 8. Read Cycle Timing
In the 8-bit bus interface mode (12/8 input wired to DIGITAL
COMMON), the address bit, AO, must be stable at least 150 ns
prior to CE going high and must remain stable during the entire
read cycle. If AO is allowed to change, damage to the AD574A
output buffers may result.
Table III. Read Timing—Full Control Mode
Symbol
Parameter
Min Typ
Max
Units
tDD
1
Access Time (from CE)
200
ns
tHD
Data Valid After CE Low
25
ns
tHL
2
Output Float Delay
100
ns
tSSR
CS
to CE Setup
150
ns
tSRR
R/C to CE Setup
0
ns
tSAR
AO to CE Setup
150
ns
tHSR
CS
Valid After CE Low
50
ns
tHRR
R/C High After CE Low
0
ns
tHAR
AO Valid After CE Low
50
ns
NOTES
1t
DD is measured with the load circuit of Figure 9 and defined as the time
required for an output to cross 0.4 V or 2.4 V.
2t
HL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 10.
a. High-Z to Logic 1
b. High-Z to Logic 0
Figure 9. Load Circuit for Access Time Test
a. Logic 1 to High-Z
b. Logic 0 to High-Z
Figure 10. Load Circuit for Output Float Delay Test
“STAND-ALONE” OPERATION
The AD574A can be used in a “stand-alone” mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability.
In this mode, CE and 12/8 are wired high, CS and AO are wired
low, and conversion is controlled by R/C. The three-state buff-
ers are enabled when R/C is high and a conversion starts when
R/C goes low. This allows two possible control signals—a high
pulse or a low pulse. Operation with a low pulse is shown in
Figure 11. In this case, the outputs are forced into the high
impedance state in response to the falling edge of R/C and return
Figure 11. Low Pulse for R/C—Outputs Enabled After
Conversion
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