參數(shù)資料
型號： AD5755-1ACPZ
廠商： Analog Devices Inc
文件頁數(shù)： 27/52頁
文件大?。?/td> 0K
描述： IC DAC 16BIT SERIAL 64LFCSP
視頻文件： AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
特色產(chǎn)品： AD5755 / AD5755-1 / AD5757 DACs
標(biāo)準(zhǔn)包裝： 1
設(shè)置時間： 11µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，4 電壓
采樣率（每秒）： *
Data Sheet
AD5755-1
Rev. E | Page 33 of 52
DATA REGISTERS
The input register is 24 bits wide. When PEC is enabled, the
input register is 32 bits wide, with the last eight bits correspond-
ing to the PEC code (see the Packet Error Checking section for
more information on PEC). When writing to a data register, the
format in Table 8 must be used.
DAC Data Register
When writing to the AD5755-1 DAC data registers, D15 to D0
are used for DAC data bits. Table 10 shows the register format
and Table 9 describes the function of Bit D23 to Bit D16.
Table 8. Writing to a Data Register
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15 to D0
R/W
DUT_AD1
DUT_AD0
DREG2
DREG1
DREG0
DAC_AD1
DAC_AD0
Data
Table 9. Input Register Decode
Bit
Description
R/W
Indicates a read from or a write to the addressed register.
DUT_AD1, DUT_AD0
Used in association with the external pins, AD1 and AD0, to determine which AD5755-1 device is being
addressed by the system controller. It is not recommended to tie both AD1 and AD0 low when using PEC, see
DUT_AD1
DUT_AD0
Function
0
Addresses part with Pin AD1 = 0, Pin AD0 = 0
0
1
Addresses part with Pin AD1 = 0, Pin AD0 = 1
1
0
Addresses part with Pin AD1 = 1, Pin AD0 = 0
1
Addresses part with Pin AD1 = 1, Pin AD0 = 1
DREG2, DREG1, DREG0
Selects whether a data register or a control register is written to. If a control register is selected, a further decode
of CREG bits (see Table 17) is required to select the particular control register, as follows.
DREG2
DREG1
DREG0
Function
0
Write to DAC data register (individual channel write)
0
1
0
Write to gain register
0
1
Write to gain register (all DACs)
1
0
Write to offset register
1
0
1
Write to offset register (all DACs)
1
0
Write to clear code register
1
Write to a control register
DAC_AD1, DAC_AD0
These bits are used to decode the DAC channel.
DAC_AD1
DAC_AD0
DAC Channel/Register Address
0
DAC A
0
1
DAC B
1
0
DAC C
1
DAC D
X
These are don’t cares if they are not relevant to the operation being performed.
Table 10. Programming the DAC Data Registers
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15 to D0
R/W
DUT_AD1
DUT_AD0
DREG2
DREG1
DREG0
DAC_AD1
DAC_AD0
DAC data
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AD5755ACPZ-REEL7 功能描述:IC DAC 16BIT QUAD 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF)
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