參數(shù)資料
型號(hào): AD5764RCSUZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/32頁(yè)
文件大?。?/td> 0K
描述: IC DAC QUAD 16BIT VOUT 32-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5764(R), AD5744R Product Change 04/Sept/2009
設(shè)計(jì)資源: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006)
標(biāo)準(zhǔn)包裝: 500
設(shè)置時(shí)間: 8µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 275 mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類(lèi)型: 4 電壓,雙極
Data Sheet
AD5764R
Rev. D | Page 25 of 32
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10). The data bits are positioned in DB15 to DB0, as shown in Table 13.
Table 13. Programming the Data Register
REG2
REG1
REG0
A2
A1
A0
DB15 to DB0
0
1
0
DAC address
16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the
data transfer takes place (see Table 10). The coarse gain register is a 2-bit register that allows the user to select the output range of each
DAC, as shown in Table 15.
Table 14. Programming the Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15 to DB2
DB1
DB0
0
1
DAC address
Don’t care
CG1
CG0
Table 15. Output Range Selection
Output Range
CG1
CG0
±10 V (Default)
0
±10.2564 V
0
1
±10.5263 V
1
0
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10). The AD5764R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC
channel by 32 LSBs to +31 LSBs in 1 LSB steps, as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale
points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register coding is
twos complement.
Table 16. Programming the Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15 to DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
DAC address
Don’t care
FG5
FG4
FG3
FG2
FG1
FG0
Table 17. Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+31 LSBs
0
1
+30 LSBs
0
1
0
No Adjustment (Default)
0
31 LSBs
1
0
1
32 LSBs
1
0
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