參數(shù)資料
型號(hào): AD5781BRUZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 23/28頁(yè)
文件大?。?/td> 0K
描述: IC DAC 18BIT SRL 20TSSOP
產(chǎn)品變化通告: AD57x1 Feature Change 27/Jul/2011
設(shè)計(jì)資源: 18-Bit Accurate, low noise, precision bipolar DC voltage source (CN0177)
標(biāo)準(zhǔn)包裝: 1,000
設(shè)置時(shí)間: 1µs
位數(shù): 18
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: *
采樣率(每秒): 1M
AD5781
Data Sheet
Rev. D | Page 4 of 28
A, B Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Midscale Glitch Impulse
3.1
nV-sec
VREFP = +10 V, VREFN = 10 V
1.7
nV-sec
VREFP = +10 V, VREFN = 0 V
1.4
nV-sec
VREFP = +5 V, VREFN = 0 V
MSB Segment Glitch Impulse6
9.1
nV-sec
VREFP = +10 V, VREFN = 10 V, see Figure 42
3.6
nV-sec
VREFP = 10 V, VREFN = 0 V, see Figure 43
1.9
nV-sec
VREFP = 5 V, VREFN = 0 V, see Figure 44
Output Enabled Glitch Impulse
45
nV-sec
On removal of output ground clamp
Digital Feedthrough
0.4
nV-sec
DC Output Impedance (Normal Mode)
3.4
k
DC Output Impedance (Output
Clamped to Ground)
6
k
Spurious Free Dynamic Range
100
dB
1 kHz tone, 10 kHz sample rate
Total Harmonic Distortion
97
dB
1 kHz tone, 10 kHz sample rate
REFERENCE INPUTS3
VREFP Input Range
5
VDD 2.5 V
V
VREFN Input Range
VSS + 2.5 V
0
DC Input Impedance
5
6.6
k
VREFP, VREFN, code dependent,
typical at midscale code
Input Capacitance
15
pF
VREFP, VREFN
LOGIC INPUTS3
Input Current8
1
+1
A
Input Low Voltage, VIL
0.3 × IOVCC
V
IOVCC = 1.71 V to 5.5 V
Input High Voltage, VIH
0.7 × IOVCC
V
IOVCC = 1.71 V to 5.5 V
Pin Capacitance
5
pF
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL
0.4
V
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
Output High Voltage, VOH
IOVCC 0.5 V
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
High Impedance Leakage Current
±1
A
High Impedance Output Capacitance
3
pF
POWER REQUIREMENTS
All digital inputs at DGND or IOVCC
VDD
7.5
VSS + 33
V
VSS
VDD 33
2.5
V
VCC
2.7
5.5
V
IOVCC
1.71
5.5
V
IOVCC ≤ VCC
IDD
4.2
5.2
mA
ISS
4
4.9
mA
ICC
600
900
A
IOICC
52
140
A
SDO disabled
DC Power Supply Rejection Ratio3, 9
±0.6
V/V
VDD ± 10%, VSS = 15 V
±0.6
V/V
VSS ± 10%, VDD = 15 V
AC Power Supply Rejection Ratio3
95
dB
VDD ± 200 mV, 50 Hz/60 Hz, VSS = 15 V
95
dB
VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1
Temperature range: 40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = 15 V, VREFP = +10 V, VREFN = 10 V.
2
Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3
Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.
4
Valid for all voltage reference spans.
5
Guaranteed by design and characterization, not production tested.
6
The AD5781 is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 , C = 143 pF (total capacitance seen by the output buffer,
lead capacitance, and so forth).
7
Includes noise contribution from AD8676BRZ voltage reference buffers.
8
Current flowing in an individual logic pin.
9
Includes PSRR of AD8676BRZ voltage reference buffers.
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