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| 型號： | AD605BRZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Dual, Low Noise, Single-Supply Variable Gain Amplifier |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | LEAD FREE, MS-012-AC, SOIC-16 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 278K |
| 代理商： | AD605BRZ-RL7 |
AD605
Rev. D | Page 14 of 20
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
1.5R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
–6.908dB
–13.82dB
–20.72dB
–27.63dB
–34.54dB
–41.45dB
–48.36dB
+IN
MID
–IN
NOTE: R = 96
1.5R = 144
175
175
0
Figure 36. R-1.5R Dual Ladder Network
DIFFERENTIAL LADDER (ATTENUATOR)
The attenuator before the fixed gain amplifier is realized by a
differential 7-stage R-1.5R resistive ladder network with an
untrimmed input resistance of 175 Ω single-ended or 350 Ω
differentially. The signal applied at the input of the ladder
network is attenuated by 6.908 dB per tap; thus, the attenuation
at the first tap is 6.908 dB, at the second, 13.816 dB, and so on
all the way to the last tap where the attenuation is 48.356 dB
(see Figure 36). A unique circuit technique is used to interpolate
continuously between the tap points, thereby providing
continuous attenuation from 0 dB to 48.36 dB. One can
think of the ladder network together with the interpolation
mechanism as a voltage-controlled potentiometer.
Since the DSX is a single-supply circuit, some means of biasing
its inputs must be provided. Node MID together with the
VOCM buffer performs this function. Without internal biasing,
external biasing is required. If not done carefully, the biasing
network can introduce additional noise and offsets. By
providing internal biasing, the user is relieved of this task and
only needs to ac couple the signal into the DSX. It should be
made clear again that the input to the DSX is still fully
differential if driven differentially, that is, Pin +IN and Pin IN
see the same signal but with opposite polarity. What changes is
the load as seen by the driver; it is 175 Ω when each input is
driven single-ended, but 350 Ω when driven differentially. This
can be easily explained when thinking of the ladder network as
two 175 Ω resistors connected back-to-back with the middle
node, MID, being biased by the VOCM buffer. A differential
signal applied between nodes +IN and IN results in zero
current into node MID, but a single-ended signal applied to
either input +IN or IN, while the other input is ac grounded,
causes the current delivered by the source to flow into the
VOCM buffer via node MID.
A feature of the X-AMP architecture is that the output-referred
noise is constant vs. gain over most of the gain range. Referring
to Figure 36, the tap resistance is approximately equal for all
taps within the ladder, excluding the end sections. The resistance
seen looking into each tap is 54.4 Ω, which makes 0.95 nV/√Hz of
Johnson noise spectral density. Because there are two attenuators,
the overall noise contribution of the ladder network is √2 times
0.95 nV/√Hz or 1.34 nV/√Hz, a large fraction of the total DSX
noise. The rest of the DSX circuit components contribute another
1.20 nV/√Hz, which together with the attenuator produces
1.8 nV/√Hz of total DSX input, referred noise.
AC COUPLING
The DSX is a single-supply circuit; therefore, its inputs need to
be ac-coupled to accommodate ground-based signals. External
Capacitor C1 and Capacitor C2 in Figure 35 level shift the input
signal from ground to the dc value established by VOCM
(nominal 2.5 V). C1 and C2, together with the 175 Ω looking
into each of DSX inputs (+IN and IN), act as high-pass filters
with corner frequencies depending on the values chosen for C1
and C2. For example, if C1 and C2 are 0.1 μF, then together
with the 175 Ω input resistance of each side of the differential
ladder of the DSX, a 3 dB high-pass corner at 9.1 kHz is formed.
If the DSX output needs to be ground referenced, then another
ac coupling capacitor is required for level shifting. This capacitor
also eliminates any dc offsets contributed by the DSX. With a
nominal load of 500 Ω and a 0.1 μF coupling capacitor, this adds a
high-pass filter with 3 dB corner frequency at about 3.2 kHz.
The choice for all three of these coupling capacitors depends on
the application. They should allow the signals of interest to pass
unattenuated, while at the same time, they can be used to limit
the low frequency noise in the system.
GAIN CONTROL INTERFACE
The gain control interface provides an input resistance of
approximately 2 MΩ at Pin VGN1 and gain scaling factors from
20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V,
respectively. The gain varies linearly in dB for the center 40 dB
of gain range, that is, for VGN equal to 0.4 V to 2.4 V for the
20 dB/V scale, and 0.25 V to 1.25 V for the 40 dB/V scale.
Figure 37 shows the ideal gain curves when the FBK-to-OUT
connection is shorted as described by the following equations:
G
(20 dB/V) = 20 ×
VGN
19,
V
REF
= 2.500 V
G
(30 dB/V) = 30 ×
VGN
19,
V
REF
= 1.6666 V
G (40 dB/V) = 40 ×
VGN
19,
V
REF
= 1.250 V
(3)
(4)
(5)
From the equations one can see that all gain curves intercept at
the same 19 dB point; this intercept is 14 dB higher (5 dB) if
the FBK-to-OUT connection is left open. Outside of the central
linear range, the gain starts to deviate from the ideal control law
but still provides another 8.4 dB of range. For a given gain
scaling, one can calculate V
REF
as
dB/V
20
V
2.500
×
=
Scale
Gain
V
REF
(6)
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