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參數(shù)資料
| 型號： | AD6140ARSRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Bandpass IF Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 109K |
| 代理商： | AD6140ARSRL |
REV. 0
–2–
AD6140–SPECIFICATIONS
(T
A
= +25
8
C, V
CC
= 2.7 V, VOLTAGE_REFERENCE_IN = 1 V, unless otherwise noted)
Specification
Conditions
Min
Typ
Max
Units
OVERALL
VOLTAGE_REFERENCE_IN = 1 V
±
5% dc,
IF = 49.6 MHz
LO = 49.792 MHz or 49.408 MHz, 200 mV p-p
Differential Input
Clock = 6.144 MHz, 800 mV p-p Differential ECL
Input, Clock Asymmetry = 50
±
2.5%
At Max Gain
At Max Gain, External Termination
At IF_INPUT (Pin 19)
At IF_INPUT (Pin 19)
6.25 kHz Bandwidth Centered at 192 kHz
Input Third Order Intercept Point
Noise Figure
Input Resistance
Input Capacitance
Dynamic Range
Maximum Gain
Minimum Gain
–27
–19
10.5
2.5
12
83
29.5
16
dBm
dB
k
pF
dB
dB
dB
76
AGC DETECTOR
AGC Threshold
Capacitor Charging Current
–24
2.8
50
dBm
μ
A
nA
AGC_TC_SELECT Input = Logic LOW (FAST AGC)
AGC_TC_SELECT Input = Logic HIGH (SLOW AGC)
ECL-TO-CMOS LEVEL
TRANSLATOR
Clock Output Drive
Clock Asymmetry
VDD (to VDD – 0.8 V) Differential Levels
5 pF Load
5 pF Load
2.6
V p-p
%
±
2.5
LNA BIAS AMPLIFIER VOLTAGE
LNA_FORCE
LNA_SENSE Input Voltage Range
2.9 V
LNA_SENSE, Minimum Gain
1.7
VDD
V
V
VDD – 0.3
POWER-DOWN INTERFACE
Logic Threshold
Turn-On Response Time
Turn-Off Response Time
0.7
100
100
V
μ
s
μ
s
To Valid Data Output
To Typical Power-Down Supply Current
POWER SUPPLY
Supply Voltage
Supply Current
Power-Down Current
Operating Temperature Range
2.5
2.9
5.75
V
mA
μ
A
°
C
Power-Down Input: Logic LOW = ON, IF_Input = 0 V
Power-Down Input: Logic HIGH = OFF
4.8
3
–40
+85
Specifications subject to change without notice.
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