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| 型號： | AD628ARMZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 0K |
| 描述： | IC AMP PGA DIFF PREC 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 放大器類型： | 電流檢測 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 0.3 V/µs |
| -3db帶寬： | 600kHz |
| 電流 - 輸入偏壓： | 1.5nA |
| 電壓 - 輸入偏移： | 150µV |
| 電流 - 電源： | 1.6mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 36 V，±2.25 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
AD628
Rev. G | Page 16 of 20
APPLICATIONS INFORMATION
GAIN ADJUSTMENT
The AD628 system gain is provided by an architecture
consisting of two amplifiers (see Figure 29). The gain of the
input stage is fixed at 0.1; the output buffer is user adjustable
as GA2 = 1 + REXT1/REXT2. The system gain is then
+
×
=
EXT2
EXT1
TOTAL
R
G
1
0.1
(1)
At a 2 nA maximum, the input bias current of the buffer amplifier
is very low and any offset voltage induced at the buffer amplifier
by its bias current may be neglected (2 nA × 10 kΩ = 20 μV).
However, to absolutely minimize bias current effects, select
REXT1 and REXT2 so that their parallel combination is 10 kΩ. If
practical resistor values force the parallel combination of REXT1
and REXT2 below 10 kΩ, add a series resistor (REXT3) to make up
for the difference. Table 5 lists several values of gain and
corresponding resistor values.
Table 5. Nearest Standard 1% Resistor Values for
Various Gains (see Figure 29)
Total Gain
(V/V)
A2 Gain
(V/V)
REXT1 (Ω)
REXT2 (Ω)
REXT3 (Ω)
0.1
1
10 k
∞
0
0.2
2
20 k
0
0.25
2.5
25.9 k
18.7 k
0
0.5
5
49.9 k
12.4 k
0
1
10
100 k
11 k
0
2
20
200 k
10.5 k
0
5
50
499 k
10.2 k
0
10
100
1 M
10.2 k
0
To set the system gain to <0.1, create an attenuator by placing
Resistor REXT4 from Pin 4 (CFILT) to the reference voltage. A
divider is formed by the 10 kΩ resistor that is in series with the
positive input of A2 and Resistor REXT4. A2 is configured for
unity gain.
Using a divider and setting A2 to unity gain yields
1
kΩ
10
0.1
/
×
+
×
=
EXT4
DIVIDER
W
R
G
INPUT VOLTAGE RANGE
VREF and the supply voltage determine the common-mode
input voltage range. The relation is expressed by
REF
S
CM
V
UPPER
10
)
V
2
.
1
–
(
11
≤
+
(2)
REF
S
CM
V
10
)
V
2
.
1
(
11
V
LOWER
+
≥
where:
VS+ is the positive supply.
VS is the negative supply.
1.2 V is the headroom needed for suitable performance.
Equation 2 provides a general formula for calculating the
common-mode input voltage range. However, keep the AD628
within the maximum limits listed in Table 1 to maintain
optimal performance. This is illustrated in Figure 30 where the
maximum common-mode input voltage is limited to ±120 V.
Figure 31 shows the common-mode input voltage bounds for
single-supply voltages.
–200
–150
–100
–50
0
50
IN
PU
T
C
O
MM
O
N
-M
O
D
E
VO
LT
A
G
E
(
V
)
100
150
200
8
6
24
010
12
SUPPLY VOLTAGE (±V)
02
99
2-
03
5
14
16
MAXIMUM INPUT COMMON-MODE
VOLTAGE WHEN VREF = GND
Figure 30. Input Common-Mode Voltage vs. Supply Voltage
for Dual Supplies
–80
–60
–40
–20
0
20
40
60
80
100
IN
PU
T
C
O
MM
O
N
-M
O
D
E
VO
LT
A
G
E
(
V
)
8
6
24
010
12
SINGLE-SUPPLY VOLTAGE (V)
02
99
2-
0
34
14
16
MAXIMUM INPUT COMMON-MODE
VOLTAGE WHEN VREF = MIDSUPPLY
Figure 31. Input Common-Mode Voltage vs.
Supply Voltage for Single Supplies
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