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參數(shù)資料
| 型號： | AD633JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Cost Analog Multiplier |
| 中文描述： | ANALOG MULTIPLIER OR DIVIDER, 1 MHz BAND WIDTH, PDIP8 |
| 封裝： | PLASTIC, MO-095AA, DIP-8 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 144K |
| 代理商： | AD633JN |
REV. B
AD633
–3–
FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to-current
converters. The product of these currents is generated by the
multiplying core. A buried Zener reference provides an overall
scale factor of 10 V. The sum of (X
×
Y)/10 + Z is then applied
to the output amplifier. The amplifier summing node Z allows
the user to add two or more multiplier outputs, convert the
output voltage to a current, and configure various analog com-
putational functions.
AD633
1
2
3
4
8
7
6
5
1
10V
X1
X2
Y1
Y2
W
Z
+V
S
–V
S
A
1
1
Figure 1. Functional Block Diagram (AD633JN
Pinout Shown)
Inspection of the block diagram shows the overall transfer func-
tion to be:
(
10
W
X
X
Y
(
Y
V
Z
=
)
)
+
1
2
1
2
(Equation 1)
ERROR SOURCES
Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 2. This scheme reduces the net error to scale
factor errors (gain error) and an irreducible nonlinearity compo-
nent in the multiplying core. The X and Y nonlinearities are
typically 0.4% and 0.1% of full scale, respectively. Scale factor
error is typically 0.25% of full scale. The high impedance Z
input should always be referenced to the ground point of the
driven system, particularly if this is remote. Likewise, the differ-
ential X and Y inputs should be referenced to their respective
grounds to realize the full accuracy of the AD633.
1k
V
300k
V
50k
V
+V
S
–V
S
50mV
TO APPROPRIATE
INPUT TERMINAL
(E.G. X
2
, X
2
, Z)
Figure 2. Optional Offset Trim Configuration
APPLICATIONS
The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
voltage controlled amplifiers, and frequency doublers. Note that
these applications show the pin connections for the AD633JN
pinout (8-lead DIP), which differs from the AD633JR pinout
(8-lead SOIC).
Multiplier Connections
Figure 3 shows the basic connections for multiplication. The X
and Y inputs will normally have their negative nodes grounded,
but they are fully differential, and in many applications the
grounded inputs may be reversed (to facilitate interfacing with
signals of a particular polarity, while achieving some desired
output polarity) or both may be driven.
W =
(X
1
– X
2
) (Y
1
– Y
2
)
10V
OPTIONAL SUMMING
INPUT, Z
+ Z
X
INPUT
0.1
m
F
+15V
–15V
8
7
6
5
1
2
3
4
AD633JN
Y1
0.1
m
F
X1
X2
Y2
–V
S
+V
S
W
Z
Y
INPUT
Figure 3. Basic Multiplier Connections
Squaring and Frequency Doubling
As Figure 4 shows, squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E
2
/10 V. The input may have either polarity, but
the output will be positive. However, the output polarity may be
reversed by interchanging the X or Y inputs. The Z input may
be used to add a further signal to the output.
0.1
m
F
+15V
E
W =
E
2
10V
8
7
6
5
1
2
3
4
AD633JN
Y1
0.1
m
F
X1
X2
Y2
–V
S
+V
S
W
Z
–15V
Figure 4. Connections for Squaring
When the input is a sine wave E sin
ω
t, this squarer behaves as a
frequency doubler, since
E
t
V
E
V
t
sin
10
cos
ω
ω
(
)
=
(
)
2
2
20
1
2
(Equation 2)
Equation 2 shows a dc term at the output which will vary
strongly with the
amplitude of the input, E. This can be avoided
using the connections shown in Figure 5, where an RC network
is used to generate two signals whose product has no dc term. It
uses the identity:
cos sin
sin
θ
θ
=
(
2
)
1
2
(Equation 3)
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參數(shù)描述 |
|---|---|
| AD633JNZ | 功能描述:IC ANALOG MULTIPLIER 8-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD633JR | 功能描述:IC ANALOG MULTIPLIER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD633JR | 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
| AD633JR-REEL | 功能描述:IC MULTIPLIER ANALOG 8-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD633JR-REEL7 | 功能描述:IC MULTIPLIER ANALOG 8-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標準包裝:25 系列:HA 功能:模擬乘法器 位元/級數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
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