參數(shù)資料
型號(hào)： AD633JR
廠商： ANALOG DEVICES INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Low Cost Analog Multiplier
中文描述： ANALOG MULTIPLIER OR DIVIDER, 1 MHz BAND WIDTH, PDSO8
封裝： PLASTIC, MS-012AA, SOIC-8
文件頁(yè)數(shù)： 4/8頁(yè)
文件大?。?/td> 144K
代理商： AD633JR
REV. B
AD633
–4–
0.1
m
F
+15V
E
W =
E
2
10V
8
7
6
5
1
2
3
4
AD633JN
Y1
0.1
m
F
X1
X2
Y2
–V
S
+V
S
W
Z
–15V
C
R
R1
1k
V
R2
3k
V
Figure 5. ”Bounceless” Frequency Doubler
At
ω
o
= 1/CR, the X input leads the input signal by 45
°
(and is
attenuated by
√
2
), and the Y input lags the X input by 45
°
(and
is also attenuated by
√
2
). Since the X and Y inputs are 90
°
out of
phase, the response of the circuit will be (satisfying Equation 3):
which
has no dc component. Resistors R1 and R2 are included to
restore the output amplitude to 10 V for an input amplitude of 10 V.
The amplitude of the output is only a weak function of fre-
quency: the output amplitude will be 0.5% too low at
ω
=
0.9
ω
o
, and
ω
o
= 1.1
ω
o
.
W
V
E
t
E
t
E
V
t
o
o
o
=
(
)
+
°
(
)
°
(
)
=
(
)
(
)
1
10
2
45
2
45
40
2
2
sin
sin
sin
ω
ω
ω
(Equation 4)
Generating Inverse Functions
Inverse functions of multiplication, such as division and square
rooting, can be implemented by placing a multiplier in the feed-
back loop of an op amp. Figure 6 shows how to implement a
square rooter with the transfer function
W
V E
=
(
10
(Equation 5)
for the condition E<0.
0.1
m
F
+15V
E
8
7
6
5
1
2
3
4
AD633JN
Y1
0.1
m
F
X1
X2
Y2
–V
S
+V
S
W
Z
–15V
W =
–(10V)E
0.1
m
F
0.1
m
F
R
10k
V
1N4148
R
10k
V
+15
–15
AD711
Figure 6. Connections for Square Rooting
0.1
m
F
+15V
E
8
7
6
5
1
2
3
4
AD633JN
Y1
0.1
m
F
X1
X2
Y2
–V
S
+V
S
W
Z
–15V
W = –10V
E
E
X
0.1
m
F
0.1
m
F
R
10k
V
1N4148
R
10k
V
+15
–15
E
X
AD711
Figure 7. Connections for Division
Likewise, Figure 7 shows how to implement a divider using a
multiplier in a feedback loop. The transfer function for the
divider is
W
V
E
E
X
=
(
)
10
(Equation 6)
0.1
m
F
+15V
8
7
6
5
1
2
3
4
AD633JN
Y1
0.1
m
F
X1
X2
Y2
–V
S
+V
S
W
Z
–15V
R1
R2
W =
(X
1
– X
2
) (Y
1
– Y
2
)
10V
1k
V
R1, R2
100k
V
+ S
X
INPUT
Y
INPUT
(R1 + R2)
R1
S
Figure 8. Connections for Variable Scale Factor
Variable Scale Factor
In some instances, it may be desirable to use a scaling voltage
other than 10 V. The connections shown in Figure 8 increase
the gain of the system by the ratio (R1 + R2)/R1. This ratio is
limited to 100 in practical applications. The summing input, S,
may be used to add an additional signal to the output or it may
be grounded.
Current Output
The AD633’s voltage output can be converted to a current
output by the addition of a resistor R between the AD633’s W
and Z pins as shown in Figure 9 below. This arrangement forms
(X
1
– X
2
) (Y
1
– Y
2
)
10V
1
R
I
O
=
X
INPUT
0.1
m
F
+15V
–15V
8
7
6
5
1
2
3
4
AD633JN
Y1
0.1
m
F
X1
X2
Y2
–V
S
+V
S
W
Z
Y
INPUT
1k
V
R
100k
V
R
Figure 9. Current Output Connections
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD633JR 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR
AD633JR-REEL 功能描述:IC MULTIPLIER ANALOG 8-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件
AD633JR-REEL7 功能描述:IC MULTIPLIER ANALOG 8-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件
AD633JRZ 功能描述:IC MULTIPLIER ANALOG 8-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件
AD633JRZ-R7 功能描述:IC MULTIPLIER ANALOG 8SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件
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