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參數(shù)資料
| 型號(hào)： | AD644S |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual High Speed, Implanted BiFET Op Amp |
| 中文描述： | 雙路高速，注入BiFET運(yùn)算放大器 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 255K |
| 代理商： | AD644S |
AD644–SPECIFICATIONS
(@ +25
8
C and V
S
=
6
15 V dc)
Model
AD644J
Min
AD644K
Min
AD644L
Min
AD644S
Min
T yp
Max
T yp
Max
T yp
Max
T yp
Max
Units
OPEN LOOP GAIN
V
O
=
±
10 V, R
L
≥
2 k
T
MIN
to T
MAX
, R
L
= 2 k
OUT PUT CHARACT ERIST ICS
Voltage @ R
L
= 2 k
, T
MIN
to T
MAX
Voltage @ R
= 10 k
, T
MIN
to T
MAX
Short Circuit Current
FREQUENCY RESPONSE
Unity Gain Small Signal
Full Power Response
Slew Rate, Unity Gain
T otal Harmonic Distortion
INPUT OFFSET VOLT AGE
1
Initial Offset
Input Offset Voltage T
MIN
to T
MAX
Input Offset Voltage vs. Supply,
T
MIN
to T
MAX
INPUT BIAS CURRENT
2
Either Input
Offset Current
MAT CHING CHARACT ERIST ICS
3
Input Offset Voltage
Input Offset Voltage T
MIN
to T
MAX
Input Bias Current
Crosstalk
INPUT IMPEDANCE
Differential
Common Mode
INPUT VOLT AGE RANGE
Differential
Common Mode
Common-Mode Rejection
INPUT NOISE
Voltage 0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
POWER SUPPLY
Rated Performance
Operating
Quiescent Current
T EMPERAT URE RANGE
Operating, Rated Performance
Storage
PACK AGE OPT ION
T O-99 Style (H-08B)
Chips
NOT ES
1
Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T
= +25
°
C.
2
Bias Current specifications are guaranteed at maximum at either input after 5 minutes of operation at T
A
= +25
°
C. For higher temperatures, the current doubles every 10
°
C.
3
Matching is defined as the difference between parameters of the two amplifiers.
4
Defined as voltage between inputs, such that neither exceeds
±
10 V from ground.
Specifications shown in
boldface
are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications
are guaranteed, although only those shown in
boldface
are tested on all production units.
Specifications subject to change without notice.
ME T ALIZAT ION PHOT OGRAPH
Dimensions shown in inches and (mm).
C ontact factory for latest dimensions.
30,000
20,000
50,000
40,000
50,000
40,000
50,000
20,000
V/V
V/V
6
10
6
12
±
12
±
13
25
6
10
6
12
±
12
±
13
25
6
10
6
12
±
12
±
13
25
6
10
6
12
±
12
±
13
25
V
V
mA
2.0
200
13.0
0.0015
2.0
200
13.0
0.0015
2.0
200
13.0
0.0015
2.0
200
13.0
0.0015
MHz
kHz
V/
μ
s
%
8.0
8.0
8.0
8.0
2.0
3.5
1.0
2.0
0.5
1.0
1.0
3.5
mV
mV
200
100
100
100
μ
V/V
10
10
75
10
5
35
10
5
35
10
5
35
pA
pA
1.0
3.5
35
0.5
2.0
25
0.25
1.0
25
0.5
3.5
35
mV
mV
pA
dB
–124
–124
–124
–124
10
12
i
6
10
12
i
3
10
12
i
6
10
12
i
3
10
12
i
6
10
12
i
3
10
12
i
6
10
12
i
3
M
i
pF
M
i
pF
±
20
±
12
±
20
±
12
±
20
±
12
±
20
±
12
V
V
dB
±
10
76
±
10
80
±
10
80
±
10
80
2
35
22
18
16
2
35
22
18
16
2
35
22
18
16
2
35
22
18
16
μ
V p-p
nV/
√
Hz
nV/
√
Hz
nV/
√
Hz
nV/
√
Hz
±
15
±
15
±
15
±
15
V
V
mA
±
5
±
18
4.5
±
5
±
18
4.5
±
5
±
18
4.5
±
5
±
18
4.5
3.5
3.5
3.5
3.5
0
–65
+70
+150
0
–65
+70
+150
0
–65
+70
+150
–55
–65
+125
+150
°
C
°
C
AD644JH
AD644JChips
AD644K H
AD644K Chips
AD644LH
AD644SH
AD644SChips
REV. A
–2–
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|---|---|
| AD6458 | GSM 3 V Receiver IF Subsystem(用于數(shù)字通的IF信號(hào)收發(fā)子系統(tǒng)) |
| AD645JN | Low Noise, Low Drift FET Op Amp |
| AD645K | Low Noise, Low Drift FET Op Amp |
| AD645KN | Low Noise, Low Drift FET Op Amp |
| AD645S | Low Noise, Low Drift FET Op Amp |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD644SH | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual High Speed, Implanted BiFET Op Amp |
| AD645 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise, Low Drift FET Op Amp |
| AD6458 | 制造商:AD 制造商全稱:Analog Devices 功能描述:GSM 3 V Receiver IF Subsystem |
| AD6458ARS | 制造商:AD 制造商全稱:Analog Devices 功能描述:GSM 3 V Receiver IF Subsystem |
| AD6459 | 制造商:AD 制造商全稱:Analog Devices 功能描述:GSM 3 V Receiver IF Subsystem |
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