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參數(shù)資料
| 型號(hào)： | AD647SH |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Ultralow Drift, Dual BiFET Op Amp |
| 中文描述： | DUAL OP-AMP, 1500 uV OFFSET-MAX, 1 MHz BAND WIDTH, MBCY8 |
| 封裝： | HERMETIC SEALED, METAL CAN, TO-99, 8 PIN |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 150K |
| 代理商： | AD647SH |
AD6472
–8–
REV. 0
C
P
80-Lead Metric Plastic Quad Flatpack
S-80A
SEATING
PLANE
0.134 (3.40)
MAX
0.041 (1.03)
0.029 (0.73)
0.004 (0.10)
MAX
0.120 (3.05)
0.100 (2.55)
0.010 (0.25)
MIN
0.015 (0.38)
0.009 (0.22)
0.690 (17.45)
0.667 (16.95)
0.555 (14.10)
0.547 (13.90)
0.486 (12.35) BSC
0
0
0
0
1
20
21
41
40
60
61
80
0
(PINS DOWN)
0.026 (0.65)
BSC
PCB Layout Recommendations
Analog and Digital
Ground Planes
Separate the analog and digital grounds.
Use a single 35 to 50 mil wide trace un-
der the device to connect the two ground
planes. Connect the IC ground pins
directly to the respective ground planes.
Use one 0.1
μ
F capacitor for each IC de-
coupling power supply connection in addi-
tion to capacitance shown in schematic.
Power Supply
Capacitors
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
t
SU
$
12ns
t
H
$
10ns
2
SCLK
SFRAME
SDATA
D6
MSB
D5
D4
D3
D2
D0
D1
X
X
X
X
X
X
X
X
D6
MSB
D5
D4
1. THE RISING EDGE OF SFRAME CAN OCCUR ANYWHERE. SFRAME MUST BE AT LEAST ONE CLOCK CYCLE WIDE.
2. SFRAME FALLING EDGE MUST OCCUR BEFORE THE SCLK RISING EDGE THAT CAPTURED THE SERIAL LSB.
THIS ENSURES CORRECT LOADING INTO THE DAC.
THE FIRST 7 BITS OF THE 16-BIT SERIAL WORD ARE THE INPUT TO THE TR DAC, MSB FIRST. THE NUMBER
SYSTEM IS TWOS COMPLEMENT, AS FOLLOWS:
FULL SCALE
MID-SCALE
MINIMUM
OUTPUT
1111111
1000000
0000000
WORD
VOLTAGE
4.5
2.5
0.5
1
X
Figure 6. Timing Recovery DAC Converter Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD647SH/883B | 制造商:Rochester Electronics LLC 功能描述:PRECISION DUAL OP AMP IC - Bulk |
| AD648 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Precision, Low Power BiFET Op Amp |
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