參數(shù)資料
型號(hào): AD660ARZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 8/20頁
文件大小: 0K
描述: IC DAC 16BIT MONO W/VREF 24-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,000
系列: DACPORT®
設(shè)置時(shí)間: 6µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 625mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
AD660
Rev. B | Page 16 of 20
In applications such as waveform generation, accurate timing of
the output samples is important to avoid noise that is induced
by jitter on the LDAC signal. In this example, the ADSP-210x
is set up to use the internal timer to interrupt the processor at
the precise and desired sample rate. When the timer interrupt
occurs, the 16-bit data word of the processor is written to the
transmit register (TXn). This causes the DSP to automatically
generate the TFS signal and begin transmission of the data.
DB0/DB8/SIN
CS
LDAC
SCLK
DT
TFS
AD660
ADSP-210x
74HC04
74HC74
SER
01
81
3-
01
9
D
Q
Figure 19. AD660 to ADSP-210x Interface
AD660 TO Z80 INTERFACE
Figure 20 shows a Zilog Z80 8-bit microprocessor connected to
the AD660 using the byte mode interface. The double-buffered
capability of the AD660 allows the microprocessor to indepen-
dently write to the low and high byte registers, and update the
DAC output. Processor speeds up to 6 MHz on the Z80 require
no extra wait states to interface with the AD660 when using a
74ALS138 as the address decoder.
The address decoder analyzes the input-output address produced
by the processor to select the function to be performed by the
AD660, qualified by the coincidence of the input/output request
(IORQ) and write (WR) pins. The least significant address bit
(A0) determines if the low or high byte register of the AD660 is
active. More significant address bits select between input register
loading, DAC output update, and unipolar or bipolar clear.
A typical Z80 software routine begins by writing the low byte of
the desired 16-bit DAC data to Address 0, followed by the high
byte to Address 1. The DAC output is then updated by activating
LDAC with a write to Address 2 (or Address 3). A clear to unipolar
zero occurs on a write to Address 4, and a clear to bipolar zero
is performed by a write to Address 5. The actual data written to
Address 2 through Address 5 is irrelevant. The decoder can easily
be expanded to control as many AD660 devices as required.
DB0 TO DB7
+VLL
CLR
LDAC
AD660
Z80
CS
Y2
A1 TO A15
A0 TO A15
D0 TO D7
Y1
E2
E1
IORQ
WR
Y0
A0
SER
HBE
DGND
01
81
3-
02
0
ADDRESS
DECODE
LBE
Figure 20. Connections for 8-Bit Bus Interface
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 V span has an LSB size of 153 μV (96 dB).
Therefore, the noise floor must remain below this level in the
frequency range of interest. The noise spectral density of the
AD660 is shown in Figure 21 and Figure 22. Figure 21 shows
the DAC output noise voltage spectral density for a 20 V span
excluding the reference. This figure shows the 1/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/√Hz.
Figure 22 shows the reference noise voltage spectral density and
shows the reference wideband noise to be below 125 nV/√Hz.
1k
100
10
1
10
100
1k
10k
100k
1M
10M
NO
IS
E
V
O
L
T
AG
E
(
n
V
/
H
z)
FREQUENCY (Hz)
01
81
3-
0
21
Figure 21. DAC Output Noise Voltage Spectral Density
1k
100
10
1
10
100
1k
10k
100k
1M
10M
NO
IS
E
V
O
L
T
AG
E
(
n
V
/
H
z)
FREQUENCY (Hz)
01
81
3-
0
22
Figure 22. Reference Noise Voltage Spectral Density
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