參數(shù)資料
型號(hào)： AD6640PCB
廠(chǎng)商： Analog Devices, Inc.
英文描述： 12-Bit, 65 MSPS IF Sampling A/D Converter
中文描述： 12位，65 MSPS的中頻采樣的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 488K
代理商： AD6640PCB
AD6640
–20–
REV. 0
faster the signal is digitized, the wider the distribution of noise.
Since the integrated noise must remain constant, the actual
noise floor is lowered by 3 dB each time the sample rate is
doubled. T he effective noise density for an ADC may be calcu-
lated by the equation:
V
NOISE rms
/
Hz
=
10
SNR
/20
4
FS
For a typical SNR of 68 dB and a sample rate of 65 MSPS, this
is equivalent to 25 nV/
√
Hz
. T his equation shows the relation-
ship between SNR of the converter and the sample rate FS.
T his equation may be used for computational purposes to deter-
mine overall receiver noise.
T he signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, the following equation accu-
rately predicts the SNR based on three terms. T hese are jitter,
average DNL error and thermal noise. Each of these terms
contributes to the noise within the converter.
Equation 1:
F
ANALOG
t
J
rms
SNR
=
±20 log 2
π
FANALOGt
J
rms
= analog input frequency
= rms jitter of the encode (rms sum of encode source
and internal encode circuitry)
ε
= average DNL of the ADC (typically 0.51 LSB)
V
NOISE rm
s
= V rms thermal noise referred to the analog input of
the ADC (typically 0.707 LSB)
)
2
+
1
+ε
2
12
2
+
VNOISE rms
2
12
2
1/2
Processing Gain
Processing gain is the improvement in signal-to-noise ratio
(SNR) gained through oversampling and digital filtering. Most
of this processing gain is accomplished using the channelizer
chips. T hese special purpose DSP chips not only provide chan-
nel selection and filtering but also provide a data rate reduction.
T he required rate reduction is accomplished through a process
called decimation. T he term decimation rate is used to indicate
the ratio of input data rate to output data rate. For example, if
the input data rate is 65 MSPS and the output data rate is
1.25 MSPS, then the decimation rate is 52.
Large processing gains may be achieved in the decimation and
filtering process. T he purpose of the channelizer, beyond tun-
ing, is to provide the narrowband filtering and selectivity that
traditionally has been provided by the ceramic or crystal filters
of a narrowband receiver. T his narrowband filtering is the
source of the processing gain associated with a wideband re-
ceiver and is simply the ratio of the passband to whole band
expressed in dB. For example, if a 30 kHz AMPS signal is
being digitized with an AD6640 sampling at 65 MSPS, the ratio
would be 0.015
MHz
/32.5
MHz
. Expressed in log form, the
processing gain is –10
×
log (0.015
MHz
/32.5
MHz
) or 33.4 dB.
Additional filtering and noise reduction techniques can be
achieved through DSP techniques; many applications do use
additional process gains through proprietary noise reduction
algorithms.
Overcoming Static Nonlinearities with Dither
T ypically, high resolution data converters use multistage
techniques to achieve high bit resolution without large com-
parator arrays that would be required if traditional “flash” ADC
techniques were employed. T he multistage converter typically
provides better wafer yields meaning lower cost and much lower
power. However, since it is a multistage device, certain portions
of the circuit are used repetitively as the analog input sweeps
from one end of the converter range to the other. Although the
worst DNL error may be less than an LSB, the repetitive nature
of the transfer function can play havoc with low level dynamic
signals. Spurious signals for a full-scale input may be –80 dBc.
However at 36 dB below full scale, these repetitive DNL errors
may cause spurious-free dynamic range (SFDR) to fall below
80 dBFS as shown in Figure 20.
A common technique for randomizing and reducing the effects
of repetitive static linearity is through the use of dither. T he
purpose of dither is to force the repetitive nature of static linear-
ity to appear as if it were random. T hen, the average linearity
over the range of dither will dominate SFDR performance. In
the AD6640, the repetitive cycle is every 15.625 mV p-p.
T o ensure adequate randomization, 5.3 mV rms is required;
this equates to a total dither power of –32.5 dBm. T his will
randomize the DNL errors over the complete range of the
residue converter. Although lower levels of dither such as that
from previous analog stages will reduce some of the linearity
errors, the full effect will only be gained with this larger dither.
Increasing dither even more may be used to reduce some of the
global INL errors. However, signals much larger than the mVs
proposed here begin to reduce the usable dynamic range of the
converter.
Even with the 5.3 mV rms of noise suggested, SNR would be
limited to 36 dB if injected as broadband noise. T o avoid this
problem, noise may be injected as an out-of-band signal. T ypically,
this may be around dc but may just as well be at FS/2 or at
some other frequency not used by the receiver. T he bandwidth
of the noise is several hundred kilohertz. By band-limiting and
controlling its location in frequency, large levels of dither may
be introduced into the receiver without seriously disrupting
receiver performance. T he result can be a marked improvement
in the SFDR of the data converter.
Figure 23 shows the same converter shown earlier but with this
injection of dither (reference Figure 20).
AD600
A
A
REF
2.2k
V
1
m
F
0.1
m
F
39
V
390
V
16k
V
+15V
NC202
NOISE
DIODE
(NoiseCom)
+5V
–5V
1k
V
2k
V
OP27
OPTIONAL HIGH
POWER DRIVE
CIRCUIT
LOW CONTROL
(0–1 VOLT)
Figure 48. Noise Source (Dither Generator)
相關(guān)PDF資料
PDF描述
AD6640ST 12-Bit, 65 MSPS IF Sampling A/D Converter
AD6644 14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644PCB 14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644ST 14-Bit, 40 MSPS/65 MSPS A/D Converter
AD6644AST-40 14-Bit, 40 MSPS/65 MSPS A/D Converter
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參數(shù)描述
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