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參數(shù)資料
| 型號(hào)： | AD664KN-BIP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Monolithic 12-Bit Quad DAC |
| 中文描述： | QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 566K |
| 代理商： | AD664KN-BIP |
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AD664
REV. C
–8–
Table II. AD664 Digital Truth Table
Function
DS1, DS0
LS
MS
TR
QS0
,
1
,
2
1
RD
CS
RST
Load 1st Rank (data)
DACA
DACB
DACC
DACD
00
01
10
11
0
0
0
0
1
1
1
1
1
1
1
1
Select Quad
Select Quad
Select Quad
Select Quad
1
1
1
1
1
→
0
1
→
0
1
→
0
1
→
0
1
1
1
1
Load 2nd Rank (data)
XX
1
1
1
XXX
1
1
→
0
1
Readback 2nd Rank (data)
Select D/A
X
1
1
Select Quad
0
1
→
0
1
Reset
XX
X
X
X
XXX
X
X
0
Transparent
1
All DACs
DACA
DACB
DACC
DACD
XX
00
01
10
11
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
000
000
000
000
000
1
1
1
1
1
1
→
0
1
→
0
1
→
0
1
→
0
1
→
0
1
1
1
1
1
Mode Select
1, 2
1st Rank
2nd Rank
XX
XX
0
1
0
0
1
1
00X
XXX
1
1
1
→
0
1
→
0
1
1
Readback Mode
1
XX
X
0
1
00X
0
1
→
0
1
Update 2nd Rank
and Mode
XX
1
0
0
XXX
1
1
→
0
1
NOTES
X = Don’t Care.
1
For 44-pin versions only. Allow the AD664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words.
2
For
MS
,
TR
,
LS
= 0, a
MS
1st write occurs.
Figure 9a. Update Output of a Single DAC
25
8
C
MIN (ns)
0
0
0
60
30
0
0
T
MIN
to T
MAX
MIN (ns)
0
0
0
80
50
0
0
SYMBOL
t
LS
*
t
DS
t
DH
t
LW
t
CH
t
AS
t
AH
*FOR t
LS
> 0, THE WIDTH OF
LS
MUST BE
INCREASED BY THE SAME AMOUNT THAT
t
LS
IS GREATER THAN 0 ns.
Figure 9b. Update Output of a Single DAC Timing
The following sections detail the timing requirements for
various data loading schemes. All of the timing specifica-
tions shown assume V
IH
= 2.4 V, V
IL
= 0.4 V, V
CC
= +15 V,
V
EE
= –15 V and V
LL
= +5 V
.
Load and Update One DAC Output
In this first example, the object is simply to change the output of
one of the four DACs on the AD664 chip. The procedure is to
select the address bits that indicate the DAC to be programmed,
pull LATCH SELECT (
LS
) low, pull CHIP SELECT (
CS
)
low, release
LS
and then release
CS
. When
CS
goes low, data
enters the first rank of the input latch. As soon as
LS
goes high,
the data is transferred into the second rank and produces the
new output voltage. During this transfer,
MS
,
TR
,
RD
and
RST
should be held high.
Preloading the First Rank of One DAC
In this case, the object is to load new data into the first rank of
one of the DACs but
not
the output. As in the previous case, the
address and data inputs are placed on the appropriate pins.
LS
is then brought to “0” and then
CS
is asserted. Note that in this
situation, however,
CS
goes high before
LS
goes high. The in-
put data is prevented from getting to the second rank and affect-
ing the output voltage.
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