參數(shù)資料
型號(hào)： AD6655
廠商： Analog Devices, Inc.
英文描述： IF Diversity Receiver
中文描述： IF分集接收機(jī)
文件頁(yè)數(shù)： 34/84頁(yè)
文件大小： 2012K
代理商： AD6655
AD6655
Rev. 0 | Page 34 of 84
75
70
65
60
55
50
45
1
10
100
1000
S
INPUT FREQUENCY (MHz)
3.00ps
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
2.00ps
2.50ps
MEASURED
0
Figure 63. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD6655.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to Application Note AN501 and Application Note AN756 for
more information about jitter performance as it relates to ADCs
(see
www.analog.com
).
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 64 through Figure 67, the power dissipated
by the AD6655 is proportional to its sample rate. In CMOS
output mode, the digital power dissipation is determined
primarily by the strength of the digital drivers and the load on
each output bit. The maximum DRVDD current (I
DRVDD
) can be
calculated by
I
DRVDD
=
V
DRVDD
×
C
LOAD
×
f
CLK
×
N
where
N
is the number of output bits (30, in the case of the
AD6655, assuming the FD bits are inactive).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency of f
CLK
/2. In practice, the DRVDD current
is established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load presented
to the output drivers can minimize digital power consumption.
The data in Figure 64 through Figure 67 was taken using the same
operating conditions as those used for the Typical Performance
Characteristics, with a 5 pF load on each output driver.
1.50
1.25
1.00
0.75
0.50
0.25
0
0.6
I
AVDD
I
DVDD
I
DRVDD
0.5
0.4
0.3
0.2
0.1
0
0
50
SAMPLE RATE (MSPS)
100
T
S
150
25
75
125
TOTAL POWER
0
Figure 64. AD6655-150 Power and Current vs. Sample Rate
1.50
1.25
1.00
0.75
0.50
0.25
0
0.6
0.5
I
AVDD
I
DVDD
I
DRVDD
0.4
0.3
0.2
0.1
0
0
75
T
S
25
50
125
100
SAMPLE RATE (MSPS)
TOTAL POWER
0
Figure 65. AD6655-125 Power and Current vs. Sample Rate
1.25
1.00
0.75
0.50
0.25
0
0.5
0.4
I
AVDD
I
DVDD
I
DRVDD
0.3
0.2
0.1
0
0
75
T
S
25
50
100
SAMPLE RATE (MSPS)
TOTAL POWER
0
Figure 66. AD6655-105 Power and Current vs. Sample Rate
相關(guān)PDF資料
PDF描述
AD6655-125EBZ1 IF Diversity Receiver
AD6655-150EBZ1 IF Diversity Receiver
AD6655BCPZ-1051 IF Diversity Receiver
AD6655BCPZ-1501 IF Diversity Receiver
AD6655BCPZ-801 IF Diversity Receiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6655-125EBZ 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796
AD6655-125EBZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver
AD6655-150EBZ 功能描述:BOARD EVAL FOR 150MSPS AD6655 RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796
AD6655-150EBZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver
AD6655ABCPZ-105 功能描述:IC IF RCVR 14BIT 105MSPS 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:*
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*