參數(shù)資料
型號: AD676JD
廠商: Analog Devices Inc
文件頁數(shù): 4/16頁
文件大小: 0K
描述: IC ADC 16BIT SAMPLING 28-CDIP
標準包裝: 1
位數(shù): 16
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 2
功率耗散(最大): 480mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 28-CDIP(0.605",15.37mm)
供應商設備封裝: 28-CDIP
包裝: 管件
輸入數(shù)目和類型: 1 個單端,雙極
配用: AD676-EB-ND - BOARD EVAL SAMPLING ADC AD676
AD676
REV. A
–12–
AD586 output, thereby optimizing the overall performance of
the AD676. It is recommended that a 10
F to 47 F high qual-
ity tantalum capacitor be tied between the VREF input of the
AD676 and ground to minimize the impedance on the
reference.
+15V
+5V
–15V
100F
AD676
10F
0.1F
78L12
79L12
0.01F
VREF
VDD
VCC
VEE
VIN
VO
NR
GND
10F
0.1F
1F
AD587
10F
15
17
18
12
16
4
2
6
8
VIN
10
10
10
Figure 7.
Using the AD676 with
±10 V input range (V
REF = 10 V) typi-
cally requires
±15 V supplies to drive op amps and the voltage
reference. If
±12 V is not available in the system, regulators
such as 78L12 and 79L12 can be used to provide power for the
AD676. This is also the recommended approach (for any input
range) when the ADC system is subjected to harsh environ-
ments such as where the power supplies are noisy and where
voltage spikes are present. Figure 7 shows an example of such a
system based upon the 10 V AD587 reference, which provides a
300
V LSB. Circuitry for additional protection against power
supply disturbances has been shown. A 100
F capacitor at each
regulator prevents very large voltage spikes from entering the
regulators. Any power line noise which the regulators cannot
eliminate will be further filtered by an RC filter (10
/10 F)
having a –3 dB point at 1.6 kHz. For best results the regulators
should be within a few centimeters of the AD676.
ANALOG INPUT
As previously discussed, the analog input voltage range for the
AD676 is
±V
REF. For purposes of ground drop and common
mode rejection, the VIN and VREF inputs each have their own
ground. VREF is referred to the local analog system ground
(AGND), and VIN is referred to the analog ground sense pin
(AGND SENSE) which allows a remote ground sense for the
input signal.
The AD676 analog inputs (VIN, VREF and AGND SENSE) ex-
hibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the corre-
sponding pin. The capacitor is disconnected when SAMPLE is
taken LOW, and the stored charge is used in the subsequent
conversion. In order to limit the demands placed on the external
source by this high initial charging current, an internal buffer
amplifier is employed between the input and this capacitance for
a few hundred nanoseconds. During this time the input pin ex-
hibits typically 20 k
input resistance, 10 pF input capacitance
and
±40 A bias current. Next, the input is switched directly to
the now precharged capacitor and allowed to fully settle. During
this time the input sees only a 50 pF capacitor. Once the sample
is taken, the input is internally floated so that the external input
source sees a very high input resistance and a parasitic input ca-
pacitance of typically only 2 pF. As a result, the only dominant
input characteristic which must be considered is the high cur-
rent steps which occur when the internal buffers are switched in
and out.
In most cases, these characteristics require the use of an external
op amp to drive the input of the AD676. Care should he taken
with op amp selection; even with modest loading conditions,
most available op amps do not meet the low distortion require-
ments necessary to match the performance capabilities of the
AD676. Figure 8 represents a circuit, based upon the AD845,
recommended for low noise, low distortion ac applications.
For applications optimized more for low bias and low offset than
speed or bandwidth, the AD845 of Figure 8 may be replaced by
the OP27.
499
1k
+12V
–12V
AD845
0.1
F
0.1
F
AGND
SENSE
±5V
INPUT
1k
AD676
15
13
14
2
3
4
7
6
V
IN
Figure 8.
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