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參數(shù)資料
| 型號(hào)： | AD679KNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SAMPLING 28-DIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 128k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 745mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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AD679
REV. D
–4–
Parameter
Symbol
Min
Max
Unit
SC Delay
tSC
50
ns
Conversion Time
tC
6.3
s
Conversion Rate
1
tCR
7.8
s
Convert Pulse Width
tCP
0.097
3.0
s
Aperture Delay
tAD
520
ns
Status Delay
tSD
0
400
ns
Access Time
2, 3
tBA
10
100
ns
10
57
4
ns
Float Delay
5
tFD
10
80
ns
Output Delay
tOD
0ns
Format Setup
tFS
100
ns
OE Delay
tOE
20
ns
Read Pulse Width
tRP
195
ns
Conversion Delay
tCD
400
ns
EOCEN Delay
tEO
50
ns
NOTES
1Includes acquisition time.
2Measured from the falling edge of
OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
3C
OUT = 100 pF.
4C
OUT = 50 pF.
5Measured from the rising edge of
OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; C
OUT
= 10 pF.
Specifications subject to change without notice.
(All device types TMIN to TMAX, VCC = +12 V
5%, VEE = –12 V
5%, VDD = +5 V
10%)
NOTES
1IN ASYNCHRONOUS MODE, STATE OF
CS DOES NOT AFFECT OPERATION.
SEE THE START CONVERSION TRUTH TABLE FOR DETAILS.
2
EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREE-
STATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.
3DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 1. Conversion Timing
Figure 2. Output Timing
NOTE
1EOC IS A THREE-STATE OUTPUT IN SYNCHRONOUS MODE
AND AN OPEN DRAIN OUTPUT IN ASYNCHRONOUS. ACCESS (tBA)
AND FLOAT (tFD) TIMING SPECIFICATIONS DO NOT APPLY IN
ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE
TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE
AND THE PULL-UP RESISTOR.
Figure 3. EOC Timing
TEST
VCP
COUT
ACCESS TIME HIGH Z TO LOGIC LOW 5V
100pF
FLOAT TIME LOGIC HIGH TO HIGH Z
0V
10pF
ACCESS TIME HIGH Z TO LOGIC HIGH
0V
100pF
FLOAT TIME LOGIC LOW TO HIGH Z
5V
10pF
IOL
IOH
DOUT
VCP
COUT
Figure 4. Load Circuit for Bus Timing Specifications
TIMING SPECIFICATIONS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD679SD | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:IC - 14-BIT SAMPLING ADC - Bulk |
| AD679SD/883B | 制造商:Rochester Electronics LLC 功能描述:IC- 14-BIT SAMPLING ADC - Bulk 制造商:Analog Devices 功能描述: |
| AD679SD/883B3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit 128 kSPS Complete Sampling ADC |
| AD679SJ | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit 128 kSPS Complete Sampling ADC |
| AD679SJ/883B | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 14-BIT 128 kSPS Complete SAMPLING RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
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