參數(shù)資料
型號(hào): AD712KRZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/20頁(yè)
文件大小: 0K
描述: IC OPAMP BIFET DUAL PREC 8SOIC
標(biāo)準(zhǔn)包裝: 98
放大器類型: J-FET
電路數(shù): 2
轉(zhuǎn)換速率: 20 V/µs
-3db帶寬: 4MHz
電流 - 輸入偏壓: 20pA
電壓 - 輸入偏移: 200µV
電流 - 電源: 5mA
電流 - 輸出 / 通道: 25mA
電壓 - 電源,單路/雙路(±): 9 V ~ 36 V,±4.5 V ~ 20 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
產(chǎn)品目錄頁(yè)面: 766 (CN2011-ZH PDF)
AD712
Rev. H | Page 13 of 20
The photos of Figure 35 and Figure 36 show the dynamic
response of the AD712 in the settling test circuit of Figure 37.
5V
5mV
500ns
100
10
0%
90
00
82
3-
0
36
5V
5mV
500ns
100
10
0%
90
0
082
3-
0
35
Figure 36. Settling Characteristics 0 V to 10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
Figure 35. Settling Characteristics 0 V to +10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
The input of the settling time fixture is driven by a flat top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2, and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
Amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
+15V
0.1F
1/2
AD712
10pF
–15V
5k
4.99k
0.47F
1/2
AD712
0.47F
200
4.99k
5 TO 18pF
0.1F
10k
10k
VIN
HP2835
20pF
1M
10k
0.2 TO 0.6pF
1.1k
5pF
205
–15V +15V
VOUT
TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
VERROR × 5
DATA
DYNAMICS
5109
(OR EQUIVALENT
FLAT TOP PULSE
GENERATION)
+
+
0
08
23
-0
37
Figure 37. Settling Time Test Circuit
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AD712KRZ 制造商:Analog Devices 功能描述:Operational Amplifier (Op-Amp) IC
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