參數(shù)資料
型號(hào): AD7142ACPZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 54/73頁(yè)
文件大?。?/td> 0K
描述: IC CAP-TO-DGTL CONV PROG 32LFCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 電容數(shù)字轉(zhuǎn)換器
分辨率(位): 16 b
采樣率(每秒): 250k
數(shù)據(jù)接口: 串行
電壓電源: 單電源
電源電壓: 2.6 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
其它名稱: AD7142ACPZ-REELDKR
AD7142
Rev. A | Page 57 of 72
BANK 3 REGISTERS
All address values are expressed in hexadecimal.
Table 49. STAGE0 Results Registers
Address
Data Bit
Default
Value
Type
Name
Description
0x0E0
[15:0]
X
R/W
STAGE0_CONV_DATA
STAGE0 CDC 16-bit conversion data
(copy of data in STAGE0_CONV_DATA register)
0x0E1
[15:0]
X
R/W
STAGE0_FF_WORD0
STAGE0 fast FIFO WORD0
0x0E2
[15:0]
X
R/W
STAGE0_FF_WORD1
STAGE0 fast FIFO WORD1
0x0E3
[15:0]
X
R/W
STAGE0_FF_WORD2
STAGE0 fast FIFO WORD2
0x0E4
[15:0]
X
R/W
STAGE0_FF_WORD3
STAGE0 fast FIFO WORD3
0x0E5
[15:0]
X
R/W
STAGE0_FF_WORD4
STAGE0 fast FIFO WORD4
0x0E6
[15:0]
X
R/W
STAGE0_FF_WORD5
STAGE0 fast FIFO WORD5
0x0E7
[15:0]
X
R/W
STAGE0_FF_WORD6
STAGE0 fast FIFO WORD6
0x0E8
[15:0]
X
R/W
STAGE0_FF_WORD7
STAGE0 fast FIFO WORD7
0x0E9
[15:0]
X
R/W
STAGE0_SF_WORD0
STAGE0 slow FIFO WORD0
0x0EA
[15:0]
X
R/W
STAGE0_SF_WORD1
STAGE0 slow FIFO WORD1
0x0EB
[15:0]
X
R/W
STAGE0_SF_WORD2
STAGE0 slow FIFO WORD2
0x0EC
[15:0]
X
R/W
STAGE0_SF_WORD3
STAGE0 slow FIFO WORD3
0x0ED
[15:0]
X
R/W
STAGE0_SF_WORD4
STAGE0 slow FIFO WORD4
0x0EE
[15:0]
X
R/W
STAGE0_SF_WORD5
STAGE0 slow FIFO WORD5
0x0EF
[15:0]
X
R/W
STAGE0_SF_WORD6
STAGE0 slow FIFO WORD6
0x0F0
[15:0]
X
R/W
STAGE0_SF_WORD7
STAGE0 slow FIFO WORD7
0x0F1
[15:0]
X
R/W
STAGE0_SF_AMBIENT
STAGE0 slow FIFO ambient value
0x0F2
[15:0]
X
R/W
STAGE0_FF_AVG
STAGE0 fast FIFO average value
0x0F3
[15:0]
X
R/W
STAGE0_PEAK_DETECT_WORD0
STAGE0 peak FIFO WORD0 value
0x0F4
[15:0]
X
R/W
STAGE0_PEAK_DETECT_WORD1
STAGE0 peak FIFO WORD1 value
0x0F5
[15:0]
X
R/W
STAGE0_MAX_WORD0
STAGE0 maximum value FIFO WORD0
0x0F6
[15:0]
X
R/W
STAGE0_MAX_WORD1
STAGE0 maximum value FIFO WORD1
0x0F7
[15:0]
X
R/W
STAGE0_MAX_WORD2
STAGE0 maximum value FIFO WORD2
0x0F8
[15:0]
X
R/W
STAGE0_MAX_WORD3
STAGE0 maximum value FIFO WORD3
0x0F9
[15:0]
X
R/W
STAGE0_MAX_AVG
STAGE0 average maximum FIFO value
0x0FA
[15:0]
X
R/W
STAGE0_HIGH_THRESHOLD
STAGE0 high threshold value
0x0FB
[15:0]
X
R/W
STAGE0_MAX_TEMP
STAGE0 temporary maximum value
0x0FC
[15:0]
X
R/W
STAGE0_MIN_WORD0
STAGE0 minimum value FIFO WORD0
0x0FD
[15:0]
X
R/W
STAGE0_MIN_WORD1
STAGE0 minimum value FIFO WORD1
0x0FE
[15:0]
X
R/W
STAGE0_MIN_WORD2
STAGE0 minimum value FIFO WORD2
0x0FF
[15:0]
X
R/W
STAGE0_MIN_WORD3
STAGE0 minimum value FIFO WORD3
0x100
[15:0]
X
R/W
STAGE0_MIN_AVG
STAGE0 average minimum FIFO value
0x101
[15:0]
X
R/W
STAGE0_LOW_THRESHOLD
STAGE0 low threshold value
0x102
[15:0]
X
R/W
STAGE0_MIN_TEMP
STAGE0 temporary minimum value
0x103
[15:0]
X
R/W
Unused
Set unused register bits = 0
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