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參數(shù)資料
| 型號： | AD7224LR-18REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT LC2MOS W/AMP 18SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 75mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 18-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 143k |
AD7224
REV. B
–7–
BIPOLAR OUTPUT OPERATION
The AD7224 can be configured to provide bipolar output op-
eration using one external amplifier and two resistors. Figure 6
shows a circuit used to implement offset binary coding. In this
case
V
O =
1
+ R2
R1
D V
REF
() – R2
R1
V
REF
()
With R1 = R2
VO = (2 D – 1) VREF
where D is a fractional representation of the digital word in
the DAC register.
Mismatch between R1 and R2 causes gain and offset errors;
therefore, these resistors must match and track over tempera-
ture. Once again, the AD7224 can be operated in single supply
or from positive/negative supplies. Table III shows the digital
code versus output voltage relationship for the circuit of Figure
6 with R1 = R2.
+15V
V
REF
R1
R2
V
OUT
R1, R2 = 10k
±0.1%
DAC
DB7
DB0
3
V
DD
V
REF
CS
WR
LDAC
RESET
V
SS
AGND
DGND
AD7224
V
OUT
DATA
(8-BIT)
Figure 6. Bipolar Output Circuit
Table III. Bipolar (Offset Binary) Code Table
DAC Register Contents
MSB
LSB
Analog Output
1 1 1 1
+V
REF
127
128
1 0 0 0
0 0 0 1
+V
REF
1
128
1 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
–V
REF
1
128
0 0 0 0
0 0 0 1
–V
REF
127
128
0 0 0 0
–V
REF
128
= –V
REF
AGND BIAS
The AD7224 AGND pin can be biased above system GND
(AD7224 DGND) to provide an offset “zero” analog output
voltage level. Figure 7 shows a circuit configuration to achieve
this. The output voltage, VOUT, is expressed as:
VOUT = VBIAS + D (VIN)
where D is a fractional representation of the digital word in
DAC register and can vary from 0 to 255/256.
For a given VIN, increasing AGND above system GND will re-
duce the effective VDD–VREF which must be at least 4 V to en-
sure specified operation. Note that VDD and VSS for the AD7224
must be referenced to DGND.
DAC
VDD
VREF
VSS
AGND
DGND
AD7224
VOUT
VIN
VBIAS
Figure 7. AGND Bias Circuit
MICROPROCESSOR INTERFACE
8085A
8088
A15
A8
ALE
AD0
AD7
ADDRESS
DECODE
LATCH
EN
AD7224*
WR
DB7
DB0
LDAC
WR
ADDRESS BUS
ADDRESS DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
CS
Figure 8. AD7224 to 8085A/8088 Interface
D0
D7
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
E OR
φ2
D0
D7
E OR
φ2
R/W
A15
A0
6809
6502
ADDRESS
DECODE
EN
ADDRESS BUS
LDAC
WR
CS
DB7
DB0
AD7224*
Figure 9. AD7224 to 6809/6502 Interface
Z-80
A15
A0
D0
D7
AD7224*
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
ADDRESS
DECODE
CS
WR
Figure 10. AD7224 to Z-80 Interface
68008
A23
A1
D0
D7
AD7224*
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
ADDRESS
DECODE
CS
R/W
DTACK
Figure 11. AD7224 to 68008 Interface
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| AD7224LRZ-18 | 功能描述:IC DAC 8BIT LC2MOS W/AMP 18SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD7224P | 制造商:Analog Devices 功能描述: |
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| AD7224TE/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
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