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參數(shù)資料
| 型號(hào)： | AD7226KNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT LC2MOS QUAD 20-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 143k |
| 產(chǎn)品目錄頁面： | 784 (CN2011-ZH PDF) |
REV.
–8–
AD7226
SPECIFICATION RANGES
In order for the DACs to operate to their specifications, the
reference voltage must be at least 4 V below the VDD power
supply voltage. This voltage differential is required for correct
generation of bias voltages for the DAC switches.
The AD7226 is specified to operate over a VDD range from
+12 V
± 5% to +15 V ± 10% (i.e., from +11.4 V to +16.5 V)
with a VSS of –5 V
± 10%. Operation is also specified for a single
+15 V
± 5% VDD supply. Applying a VSS of –5 V results in
improved zero code error, improved output sink capability with
outputs near AGND and improved negative-going settling time.
Performance is specified over a wide range of reference voltages
from 2 V to (VDD – 4 V) with dual supplies. This allows a range
of standard reference generators to be used such as the AD780,
a 2.5 V band gap reference and the AD584, a precision 10 V
reference. Note that in order to achieve an output voltage range
of 0 V to 10 V a nominal 15 V
± 5% power supply voltage is
required by the AD7226.
SETTLING TIME
The output stage of the buffer amplifiers consists of a bipolar
NPN transistor from the VDD line and a constant current load to
VSS. VSS is the negative power supply for the output buffer ampli-
fiers. As mentioned in the op amp section, in single supply
operation the NMOS transistor will come out of saturation as the
output voltage approaches AGND and will act as a resistive load
of approximately 2 k
W to AGND. As a result, the settling time for
negative-going signals approaching AGND in single supply opera-
tion will be longer than for dual supply operation where the
current load of 400
mA is maintained all the way down to AGND.
Positive-going settling-time is not affected by VSS.
The settling-time for the AD7226 is limited by the slew-rate of
the output buffer amplifiers. This can be seen from Figure 6
which shows the dynamic response for the AD7226 for a full
scale change. Figures 7a and 7b show expanded settling-time
photographs with the output waveforms derived from a differen-
tial input to an oscilloscope. Figure 7a shows the settling time
for a positive-going step and Figure 7b shows the settling time
for a negative-going output step.
DATA
VOUT
Figure 6. Dynamic Response (VSS = –5 V)
DATA
O/P
+1/2 LSB
–1/2 LSB
Figure 7a. Positive Step Settling Time (VSS = –5 V)
DATA
O/P
+1/2 LSB
–1/2 LSB
Figure 7b. Negative Step Settling Time (VSS = –5 V)
GROUND MANAGEMENT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. This is especially true in micropro-
cessor systems where digital noise is prevalent. The simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7226. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7226 AGND and
DGND pins (IN914 or equivalent).
Unipolar Output Operation
This is the basic mode of operation for each channel of the
AD7226, with the output voltage having the same positive
polarity as +VREF. The AD7226 can be operated single supply
(VSS = AGND) or with positive/negative supplies (see op amp
section which outlines the advantages of having negative VSS).
The code table for unipolar output operation is shown in Table
II. Note that the voltage at VREF must never be negative with
respect to DGND in order to prevent parasitic transistor turn-on.
Connections for the unipolar output operation are shown in
Figure 8.
D
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