參數(shù)資料
型號： AD7233AN
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： ; Series:M; Thermistor Type:NTC; Resistance:100kohm; Package/Case:Radial; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; R/T Curve:4 RoHS Compliant: No
中文描述： SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDIP8
封裝： MINI, PLASTIC, DIP-8
文件頁數(shù)： 2/8頁
文件大?。?/td> 99K
代理商： AD7233AN
REV. A
–2–
AD7233–SPECIFICATIONS
1
(V
DD
= +12 V to +15 V,
2
V
SS
= –12 V to –15 V,
2
GND = 0 V, R
L
= 2 k
C
L
= 100 pF to GND. All specifications T
MIN
to T
MAX
unless otherwise noted.)
,
Parameter
A, B
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy
3
Differential Nonlinearity
3
Bipolar Zero Error
3
Full-Scale Error
3
Full-Scale Temperature Coefficient
4
12
±
1
±
0.9
±
6
±
8
±
30
Bits
LSB max
LSB max
LSB max
LSB max
ppm of FSR/
°
C typ
Guaranteed Monotonic
DAC Latch Contents 0000 0000 0000
Guaranteed By Process
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
IN
Input Capacitance
4
2.4
0.8
V min
V max
±
1
8
μ
A max
pF max
V
IN
= 0 V to V
DD
ANALOG OUTPUTS
Output Voltage Range
DC Output Impedance
4
±
5
0.5
V
typ
AC CHARACTERISTICS
4
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
3
Digital Feedthrough
3
Settling Time to Within
±
1/2 LSB of Final Value
Typically 4
μ
s; DAC Latch 100. . .000 to 011. . .111
Typically 5
μ
s; DAC Latch 011. . .111 to 100. . .000
DAC Latch Contents Toggled Between All 0s and all 1s
LDAC
= High
10
10
30
10
μ
s max
μ
s max
nV secs typ
nV secs typ
POWER REQUIREMENTS
V
DD
Range
V
SS
Range
I
DD
I
SS
+10.8/+16.5
–10.8/–16.5
10
2
V min/V max
V min/V max
mA max
mA max
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; Typically 7 mA at Thresholds
Output Unloaded; Typically 1 mA at Thresholds
NOTES
1
Temperature Ranges are as follows: A, B Versions: –40
°
C to +85
°
C.
2
Power Supply Tolerance: A, B Versions:
±
10%.
3
See Terminology.
4
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
Limit at +25 C, T
MIN
, T
MAX
(All Versions)
Parameter
Unit
Conditions/Comments
t
13
t
2
t
3
t
4
t
5
t
6
t
7
t
8
200
15
70
0
40
0
20
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SYNC
to SCLK Falling Edge Setup Time
SYNC
to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC
High to
LDAC
Low
LDAC
Pulsewidth
LDAC
High to
SYNC
Low
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
SCLK Mark/Space Ratio range is 40/60 to 60/40.
(V
DD
= +10.8 V to +16.5 V, V
SS
= –10.8 V to –16.5 V, GND = O V, R
L
= 2 k
C
L
= 100 pF. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
,
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