(VDD = +12 V to +15 V,
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AD7237ABRZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 5/12闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DAC 12BIT LC2MOS DUAL 24-SOIC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Data Converter Fundamentals
DAC Architectures
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� DACPORT®
瑷�(sh猫)缃檪(sh铆)闁擄細 8µs
浣嶆暩(sh霉)锛� 12
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 骞惰伅(li谩n)
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 2
闆诲闆绘簮锛� 闆� ±
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 24-SOIC锛�0.295"锛�7.50mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 24-SOIC W
鍖呰锛� 绠′欢
杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� 2 闆诲锛屽柈妤�锛�2 闆诲锛岄洐妤�
閲囨ǎ鐜囷紙姣忕锛夛細 *
REV. 0
鈥�2鈥�
AD7237A/AD7247A鈥揝PECIFICATIONS
(VDD = +12 V to +15 V,
1 V
SS = 0 V or 鈥�12 V to 鈥�15 V,
1 AGND =
DGND = 0 V [AD7237A], GND = 0 V [AD7247A], REF IN = +5 V,
Parameter
A
2
B
2
T
2
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
Bits
Relative Accuracy
3
卤1
卤1/2
LSB max
Differential Nonlinearity
3
卤0.9
LSB max
Guaranteed Monotonic
Unipolar Offset Error
3
卤3
卤4
LSB max
VSS = 0 V or 鈥�12 V to 鈥�15 V
4. DAC Latch Contents All 0s
Bipolar Zero Error
3
卤6
卤4
卤6
LSB max
VSS = 鈥�12 V to 鈥�15 V
4. DAC Latch Contents
1000 0000 0000
Full-Scale Error
3, 5
卤5
卤6
LSB max
Full-Scale Mismatch
5
卤1
LSB typ
REFERENCE OUTPUT
REF OUT
4.97/5.03
4.95/5.05
V min/max
Reference Temperature
Coefficient
卤25
ppm/
掳C typ
Reference Load Change
(
REF OUT vs. I)
鈥�1
mV max
Reference Load Current Change (0-100
A)
REFERENCE INPUT
Reference Input Range
4.75/5.25
V min/max
5 V
卤 5%
Input Current
6
卤5
A max
DIGITAL INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Current
IIN (Data Inputs)
卤10
A max
VIN = 0 V to VDD
Input Capacitance
6
8
pF max
ANALOG OUTPUTS
Output Range Resistors
15/30
k
min/max
Output Voltage Ranges
7
+5, +10
V
Single Supply; (VSS = 0 V)
Output Voltage Ranges
7
+5, +10,
卤5 +5, +10, 卤5 +5, +10, 卤5
Dual Supply; (VSS = 鈥�12 V to 鈥�15 V
4)
DC Output Impedance
0.5
typ
AC CHARACTERISTICS
6
Voltage Output Settling Time
Settling Time to Within
卤1/2 LSB of Final Value
Positive Full-Scale Change
8
10
s max
DAC Latch all 0s to all 1s. Typically 5
s
Negative Full-Scale Change 8
8
10
s max
DAC Latch all 1s to all 0s. Typically 5
s
VSS = 鈥�12 V to 鈥�15 V
4.
Digital-to-Analog Glitch
Impulse
3
30
nV secs typ
DAC Latch Contents Toggled Between all 0s and all 1s
Digital Feedthrough
3
10
nV secs typ
Digital Crosstalk
3
30
nV secs typ
POWER REQUIREMENTS
VDD
+10.8/+16.5 +11.4/+15.75 +11.4/+15.75 V min/max
For Specified Performance Unless Otherwise Stated
VSS
鈥�10.8/鈥�16.5
鈥�11.4/鈥�15.75 鈥�11.4/鈥�15.75
V min/max
For Specified Performance Unless Otherwise Stated
IDD
15
mA max
Output Unloaded. Typically 10 mA
ISS (Dual Supplies)
5
mA max
Output Unloaded. Typically 3 mA
NOTES
1Power Supply tolerance is
卤10% for A version and 卤5% for B and T versions.
2Temperature ranges are as follows: A, B Versions, 鈥�40
掳C to +85掳C; T Version, 鈥�55掳C to +125掳C.
3See Terminology.
4With appropriate power supply tolerances.
5Measured with respect to REF IN and includes unipolar/bipolar offset error.
6Sample tested @ +25
掳C to ensure compliance.
70 V to +10 V range is only available with V
DD
鈮� 14.25 V.
Specifications subject to change without notice.
RL = 2 k, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AD7237ABRZ-REEL 鍔熻兘鎻忚堪:IC DAC 12BIT DUAL W/BUFF 24-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:DACPORT® 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤碉紱1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k
AD7237AQ 鍔熻兘鎻忚堪:IC DAC 12BIT W/AMP W/BUFF 24CDIP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:DACPORT® 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:1µs 浣嶆暩(sh霉):8 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:8 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:941mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:8 闆诲锛屽柈妤� 閲囨ǎ鐜囷紙姣忕锛�:*
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AD7237ATQ/883B 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:12-Bit Digital-to-Analog Converter
AD7237BQ 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

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