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參數(shù)資料
| 型號(hào)： | AD7237KN |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT LC2MOS DUAL 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
AD7237A/AD7247A
REV. 0
–12–
C1744–24–3/93
PRINTED
IN
U.S.A.
Either high byte or low byte data can be written first to the in-
put latch. A write to the AD7237A DAC Latch address transfers
the data from the input latches to the respective DAC latches
and updates both analog outputs. Alternatively, the LDAC in-
put can be asynchronous or can be common to a number of
AD7237As for simultaneous updating of a number of voltage
channels.
AD7237A—68008 Interface
An interface between the AD7237A and the 68008 is shown in
Figure 14. In the diagram shown, the LDAC is derived from an
asynchronous LDAC signal, but this can be derived from the
address decoder as in the previous interface diagram.
Figure 14. AD7237A to 68008 Interface
AD7237A—6502/6809 Interface
Figure 15 shows an interface between the AD7237A and the
6502 or 6809 microprocessor. The procedure for writing data to
the AD7237A is as outlined for the 8085A/8088 interface. For
the 6502 microprocessor, the
2 clock is used to generate the
WR
, while for the 6809 the E signal is used.
Figure 15. AD7237A to 6502/6809 Interface
OUTLINE DIMENSIONS
Dimensions shown in inchcs and (mm).
Plastic DIP (N-24)
Cerdip (Q-24)
SOIC (R-24)
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