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參數(shù)資料
| 型號： | AD7243BR |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT W/AMP W/REF 16-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 47 |
| 系列： | DACPORT® |
| 設置時間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 300k |
REV. A
–5–
AD7243
TERMINOLOGY (Continued)
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the out-
put voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7243 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from
VOUT with all zeros loaded into the DAC latch when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
PIN CONFIGURATION
DIP and SOIC
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
REFIN
REFOUT
CLR
BIN/COMP
SCLK
SDIN
SYNC
DGND
AGND
SDO
DCEN
LDAC
VDD
VSS
VOUT
ROFS
AD7243
CIRCUIT INFORMATION
D/A Section
The AD7243 contains a 12-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The output voltage
from the converter has the same polarity as the reference volt-
age, REFIN, allowing single supply operation.
SHOWN FOR ALL 1S
ON DAC
*BUFFERED REFIN VOLTAGE
2R
R
2R
DB0
DB1
DB9
DB10
DB11
REFIN*
AGND
R
OFS
VOUT
Figure 2. D/A Simplified Circuit Diagram
Internal Reference
The AD7243 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V
± 50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter (by connecting the REFOUT pin to the REFIN pin.)
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500
A to an ex-
ternal load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference is re-
quired for external use with capacitive loads greater than 50 pF
then it should be decoupled to AGND with a 200
resistor in
series with a parallel combination of a 10
F tantalum capacitor
and a 0.1
F ceramic capacitor.
200
10 F
0.1 F
REFOUT
EXT
LOAD
Figure 3. Reference Decoupling Scheme
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7243. References
such as the AD586 provide an ideal external reference source
(see Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
degradation in linearity vs. REFIN.
REFIN – Volts
1.0
2
LINEARITY
ERROR
–
LSBs
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3
4567
8
9
VDD = +15V
VSS = –15V
TA = +25 C
INL
DNL
Figure 4. Typical Linearity vs. REFIN Voltage
Op Amp Section
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The ROFS input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
of developing +10 V across a 2 k
load to AGND.
The output amplifier can be operated from a single +12 V to
+15 V supply by tying VSS = 0 V.
The amplifier can also be operated from dual supplies to allow
an additional bipolar output range of –5 V to +5 V. Dual supplies are
necessary for the bipolar output range but can also be used for
the unipolar ranges to give faster settling time to voltages near
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