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參數(shù)資料
| 型號(hào)： | AD7243BRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SRL DAC 12BIT LC2MOS 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 300k |
AD7243
–6–
REV. A
0 V, to allow full sink capability of 2.5 mA over the entire
output range and to eliminate the effects of negative offsets on
the transfer characteristic (outlined previously). A plot of the
output sink capability of the amplifier is shown in Figure 5.
3
2
1
0
2
4
68
10
OUTPUT VOLTAGE – Volts
V
= –15V
SS
V
= 0V
SS
I
–
mA
SINK
Figure 5. Amplifier Sink Current
DIGITAL INTERFACE
The AD7243 contains an input serial to parallel shift register
and a DAC latch. A simplified diagram of the input loading
DAC LATCH (12 BITS)
INPUT SHIFT REGISTER (16 BITS)
GATING
SIGNAL
GATED
SCLK
SDO
RESET
EN
÷16
COUNTER/
DECODER
AUTO – UPDATE
CIRCUITRY
DCEN
SYNC
SCLK
SDIN
LDAC
CLR
Figure 6. Simplified Loading Structure
SCLK
DB11
MSB
DB14
*
DB13
*
DB12
*
DB0
LSB
* = DON'T CARE
t
1
t
2
t
3
t
4
t
5
SDIN
SYNC
LDAC
CLR
DB15
*
t
6
t
7
t
8
t
9
Figure 7. Timing Diagram (Standalone Mode)
circuitry is shown in Figure 6. Serial data on the SDIN input is
loaded to the input register under control of DCEN,
SYNC and
SCLK. When a complete word is held in the shift register, it
may then be loaded into the DAC latch under control of
LDAC. Only the data in the DAC latch determines the analog
output on the AD7243.
The DCEN (daisy-chain enable) input is used to select either a
standalone mode or a daisy-chain mode. The loading format is
slightly different depending on which mode is selected.
Serial Data Loading Format (Standalone Mode)
With DCEN at Logic 0 the standalone mode is selected. In this
mode a low
SYNC input provides the frame synchronization
signal which tells the AD7243 that valid serial data on the SDIN
input will be available for the next 16 falling edges of SCLK. An
internal counter/decoder circuit provides a low gating signal so
that only 16 data bits are clocked into the input shift register.
After 16 SCLK pulses the internal gating signal goes inactive
(high) thus locking out any further clock pulses. Therefore, ei-
ther a continuous clock or a burst clock source may be used to
clock in the data.
The
SYNC input should be taken high after the complete 16-bit
word is loaded in.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD7243SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STANDARD MICROCIRCUIT DRAWING |
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| AD7243SQ883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STANDARD MICROCIRCUIT DRAWING |
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