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參數(shù)資料
| 型號： | AD7243BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SRL LC2MOS 16SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 47 |
| 系列： | DACPORT® |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 300k |
AD7243–SPECIFICATIONS
Parameter
A
2
B
2
S
2
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
Bits
Relative Accuracy
3
±1
±1/2
±1
LSB max
Differential Nonlinearity
3
±0.9
LSB max
Guaranteed Monotonic
Unipolar Offset Error
3
±4
±5
LSB max
VSS = 0 V or –12 V to –15 V
1; DAC Latch
Contents All 0s
Bipolar Zero Error
3
±5
±6
LSB max
VSS = –12 V to –15 V
1; DAC Latch Contents All 0s
Full-Scale Error
3, 4
±6
±7
LSB max
Full-Scale Temperature Coefficient
5
±5
ppm of FSR/
Guaranteed By Process
°C typ
REFERENCE OUTPUT
Reference Output Range, REFOUT
4.95/5.05
V min/V max
Reference Temperature Coefficient
5
±25
±30
ppm/
°C typ
Guaranteed By Process
Reference Load Change
(
REFOUT VS. IL)
–1
mV max
Reference Load Current (IL) Change (0–100
A)
REFERENCE INPUT
Reference Input Range, REFIN
4.95/5.05
V min/V max
5 V
±1% for Specified Performance
Input Current
5
A max
DIGITAL INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Current, IIN
±1
A max
VIN = 0 V to VDD
Input Capacitance
5
8
pF max
DIGITAL OUTPUT
Serial Data Out (SDO)
Output Low Voltage, VOL
0.4
V max
ISINK = 1.6 mA
Output High Voltage, VOH
4.0
V min
ISOURCE = 400
A
ANALOG OUTPUT
Output Range Resistor, ROFS
15/30
k
min/max
Typically 20 k . Guaranteed By Process
Output Voltage Ranges
6
+5, +10
V
Single Supply; VSS = 0 V
Output Voltage Ranges
6
+5, +10,
±5 +5, +10, ±5 +5, +10, ±5
V
Dual Supply; VSS = –12 V to –15 V
DC Output Impedance
5
0.5
typ
AC CHARACTERISTICS
5
Voltage Output Settling-Time
Settling Time to Within
±1/2 LSB of Final Value
Positive Full-Scale Change
10
s max
Typically 4
s
Negative Full-Scale Change
10
s max
Typically 5
s
Digital-to-Analog Glitch Impulse
3
30
nV secs typ
DAC Latch Contents Toggled Between All 0s
and All 1s
Digital Feedthrough
3
10
nV secs typ
LDAC = High
POWER REQUIREMENTS
VDD Range
+10.8/+16.5 +10.8/+16.5
+11.4/+15.75
V min/V max
For Specified Performance Unless Otherwise Stated
VSS Range (Dual Supplies)
–10.8/–16.5
–11.4/–15.75
V min/V max
For Specified Performance Unless Otherwise Stated
IDD
10
mA max
Output Unloaded; Typically 7 mA
ISS (Dual Supplies)
2
mA max
Output Unloaded; Typically 1 mA
NOTES
1Power Supply Tolerance A, B Versions:
±10%; S Version: ±5%.
2Temperature ranges are as follows: A, B Versions: –40
°C to +85°C; S Version: –55°C to +125°C.
3See terminology.
4Measured with respect to REFIN and includes unipolar/bipolar offset error.
5Guaranteed by design and characterization, not production tested.
60 V to +10 V output range is available only with V
DD
≥ +14.25 V.
Specifications subject to change without notice.
(VDD = +12 V to +15 V,
1 V
SS = 0 V or –12 V to –15 V,
1 AGND = DGND = O V, REFIN = +5 V,
RL = 2 k , CL = 100 pF to AGND. All Specifications TMIN to TMAX unless otherwise noted.)
–2–
REV. A
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