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參數(shù)資料
| 型號： | AD7244JRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT LC2MOS DUAL 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 195mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 250k |
AD7242/AD7244
REV. A
–4–
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7242/AD7244 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
(J, K, A, B Versions)
(S Version)
Units
Conditions/Comments
t1
50
ns min
TFS
to TCLK Falling Edge
t2
75
100
ns min
TCLK Falling Edge to TFS
t3
3
150
200
ns min
TCLK Cycle Time
t4
30
40
ns min
Data Valid to TCLK Setup Time
t5
75
100
ns min
Data Valid to TCLK Hold Time
t6
40
ns min
LDAC
Pulse Width
NOTES
1Timing specifications are sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a volt-
age level of 1.6 V.
2See Figure 6.
3TCLK Mark/Space ratio is 40/60 to 60/40.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25
°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
REF OUT to AGND . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
REF INA, REF INB to AGND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
J, K Versions
AD7244 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
°C to +70°C
AD7242 . . . . . . . . . . . . . . . . . . . . . . . . . –40
°C to +85°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40
°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55
°C to +125°C
(VDD = +5 V
5%, VSS = –5 V
5%, AGND = DGND = 0 V)
PIN CONFIGURATIONS
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
°C
Power Dissipation (Any Package) to +75
°C . . . . . . . 550 mW
Derates above +75
°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DIP
SOIC
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