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參數(shù)資料
| 型號(hào)： | AD7245AQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT W/REF 24-CDIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-CDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
A
2
B
2
T
2
Parameter
Version
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
Bits
Relative Accuracy @ 25
°C3
±3/4
±1/2
LSB max
TMIN to TMAX
±1
±3/4
LSB max
TMIN to TMAX
±1/2
LSB max
VDD = 15 V
± 10%
Differential Nonlinearity
3
±1
LSB max
Guaranteed Monotonic
Unipolar Offset Error @ 25
°C3
±3
LSB max
VSS = 0 V or –12 V to –15 V
4
TMIN to TMAX
±5
LSB max
Typical Tempco is
±3 ppm of FSR5/°C.
Bipolar Zero Error @ 25
°C3
±3
±2
LSB max
ROFS connected to REF OUT; VSS = –12 V to –15 V
4
TMIN to TMAX
±5
±4
LSB max
Typical Tempco is
±3 ppm of FSR5/°C.
DAC Gain Error
3, 6
±2
LSB max
Full-Scale Output Voltage Error
7 @ 25
°C ±0.2
±0.2
% of FSR max
VDD = 15 V
Full Scale/VDD
±0.06
% of FSR/V max
VDD = +12 V to +15 V
4
Full Scale/VSS
±0.01
% of FSR/V max
VSS = –12 V to –15 V
4
Full-Scale Temperature Coefficient
8
±40
±30
±40
ppm of FSR/
°C max V
DD = 15 V
REFERENCE OUTPUT
REF OUT @ 25
°C
4.99/5.01 4.99/5.01
4.99/5.01 V min/V max
VDD = 15 V
REF OUT/VDD
2
mV/V max
VDD = 12 V to 15 V
4
Reference Temperature Coefficient
±25
±35
ppm/
°C typ
Reference Load Change
(
REF OUT vs. I)
–1
mV max
Reference Load Current Change (0–100
A)
DIGITAL INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Current, IIN
±10
A max
VIN = 0 V to VDD
Input Capacitance
9
8
pF max
ANALOG OUTPUTS
Output Range Resistors
15/30
k
min/k max
Output Voltage Ranges
10
5, 10
V
VSS = 0 V; Pin Strappable
5, 10,
VSS = –12 V to –15 V;
4 Pin Strappable
±5
±5V
DC Output Impedance
0.5
typ
AC CHARACTERISTICS
9
Voltage Output Settling Time
Settling Time to Within
±1/2 LSB of Final Value
Positive Full-Scale Change
7
10
s max
DAC Latch All 0s to All 1s
Negative Full-Scale Change
7
10
s max
DAC Latch All 1s to All 0s; VSS = –12 V to –15 V
4
Output Voltage Slew Rate
2
1.5
V/
s min
Digital Feedthrough
3
10
nV-s typ
Digital-to-Analog Glitch Impulse
30
nV-s typ
POWER REQUIREMENTS
VDD
+10.8/
V min/
For Specified Performance Unless Otherwise Stated
+16.5
V max
VSS
–10.8/
V min/
For Specified Performance Unless Otherwise Stated
–16.5
V max
IDD @ 25
°C
9
mA max
Output Unloaded; Typically 5 mA
TMlN to TMAX
10
12
mA max
Output Unloaded
ISS (Dual Supplies)
3
5
mA max
Output Unloaded; Typically 2 mA
NOTES
1Power supply tolerance is
±10%.
2Temperature ranges are as follows: A/B Versions; –40
°C to +85°C; T Version; –55°C to +125°C.
3See Terminology.
4With appropriate power supply tolerances.
5FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and
± 5 V output ranges.
6This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.
7This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and
±5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V
range. It includes the effects of internal voltage reference, gain and offset errors.
8Full-Scale TC =
FS/T, where FS is the full-scale change from T
A = 25
°C to T
MIN or TMAX.
9Guaranteed by design and characterization, not production tested.
100 V to 10 V output range is available only when V
DD
≥ +14.25 V.
Specifications subject to change without notice.
AD7245A/AD7248A–SPECIFICATIONS
REV. B
–2–
(VDD = +12 V to +15 V,
1 V
SS = O V or –12 V to –15 V,
1
AGND = DGND = O V, RL = 2 k , CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
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