lVSS
參數(shù)資料
型號: AD7245JPZ
廠商: Analog Devices Inc
文件頁數(shù): 12/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT LC2MOS 28-PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 39
系列: DACPORT®
設(shè)置時間: 7µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
功率耗散(最大): 210mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
AD7245A/AD7248A
REV. B
–5–
AD7245A PIN FUNCTION DESCRIPTIONS
(DIP PIN NUMBERS)
Pin
Mnemonic Description
lVSS
Negative Supply Voltage (0 V for single
supply operation).
2ROFS
Bipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.
3
REF OUT
Reference Output. The on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.
4
AGND
Analog Ground.
5
DB11
Data Bit 11. Most Significant Bit (MSB).
6–11
DB10–DB5 Data Bit 10 to Data Bit 5.
12
DGND
Digital Ground.
13–16 DB4–DB1
Data Bit 4 to Data Bit 1.
17
DB0
Data Bit 0. Least Significant Bit (LSB).
18
CS
Chip Select Input (Active LOW). The
device is selected when this input is active.
Pin
Mnemonic
Description
19
WR
Write Input (Active LOW). This is used in
conjunction with
CS to write data into the
input latch of the AD7245A.
20
LDAC
Load DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.
21
CLR
Clear Input (Active LOW). When this
input is active the contents of the DAC
latch are reset to all 0s.
22
VDD
Positive Supply Voltage.
23
RFB
Feedback Resistor. This allows access to
the amplifier’s feedback loop.
24
VOUT
Output Voltage. Three different output
voltage ranges can be chosen: 0 V to 5 V,
0 V to 10 V or –5 V to +5 V.
AD7245A PIN CONFIGURATIONS
DIP and SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AD7245A
TOP VIEW
(NOT TO SCALE)
VSS
ROFS
REF OUT
AGND
(MSB) DB11
DB10
DB9
DB8
DB7
DB6
DB5
DGND
DB4
DB3
DB2
DB1
DB0 (LSB)
CS
WR
LDAC
CLR
VDD
RFB
VOUT
LCCC
4
3
2
1 28 27 26
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12 13 14 15 16 17 18
AGND
DB11
DB10
NC
DB9
DB8
DB7
DB6
DB5
DGND
NC
DB4
DB3
DB2
CLR
LDAC
WR
NC
CS
DB0
DB1
REF
OUT
R
OFS
V
SS
NC
V
OUT
R
FB
V
DD
NC = NO CONNECT
AD7245A
TOP VIEW
(NOT TO SCALE)
PLCC
1
2
3
4
5
6
7
AGND
DB11
DB10
NC
DB9
DB8
DB7
25
24
23
22
21
20
19 DB1
DB0
CS
NC
WR
LDAC
CLR
18
17
16
15
14
13
12
DB2
DB3
DB4
NC
DGND
DB5
DB6
V
DD
R
FB
V
OUT
NC
V
SS
R
OFS
REF
OUT
AD7245A
TOP VIEW
(NOT TO SCALE)
NC = NO CONNECT
8
9
10
11
26
27
28
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