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參數(shù)資料
| 型號(hào)： | AD7247ABR |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT LC2MOS DUAL 24SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 1W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
AD7237A/AD7247A
REV. 0
–4–
AD7237A PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS)
Pin
Mnemonic
Description
1
REF INA
Voltage Reference Input for DAC A. The reference voltage for DAC A is applied to this pin. It is internally
buffered before being applied to the DAC. The nominal reference voltage for correct operation of the
AD7237A is 5 V.
2
REF OUT
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part with
internal reference, REF OUT should be connected to REF INA, REF INB.
3
REF INB
Voltage Reference Input for DAC B. The reference voltage for DAC B is applied to this pin. It is internally
buffered before being applied to the DAC. The nominal reference voltage for correct operation of the
AD7237A is 5 V.
4ROFSB
Output Offset Resistor for DAC B. This input configures the output ranges for DAC B. It is connected to
VOUTB for the +5 V range, to AGND for the +10 V range and to REF INB for the
±5 V range.
5VOUTB
Analog Output Voltage from DAC B. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and
±5 V. The amplifier is capable of developing
+10 V across a 2 k
resistor to GND.
6
AGND
Analog Ground. Ground reference for DACs, reference and output buffer amplifiers.
7
DB7
Data Bit 7.
8-10
DB6-DB4
Data Bit 6 to Data Bit 4.
11
DB3
Data Bit 3/Data Bit 11 (MSB).
12
DGND
Digital Ground. Ground reference for digital circuitry.
13
DB2
Data Bit 2/Data Bit 10.
14
DB1
Data Bit 1/Data Bit 9.
15
DB0
Data Bit 0 (LSB)/Data Bit 8.
16
A0
Address Input. Least significant address input for input latches. A0 and A1 select which of the four input
latches data is written to (see Table II).
17
A1
Address Input. Most significant address input for input latches.
18
CS
Chip Select. Active low logic input. The device is selected when this input is active.
19
WR
Write Input. WR is an active low logic input which is used in conjunction with CS, A0 and A1 to write data
to the input latches.
20
LDAC
Load DAC. Logic input. A new word is loaded into the DAC latches from the respective input latches on the
falling edge of this signal.
21
VDD
Positive Supply (+12 V to +15 V).
22
VOUTA
Analog Output Voltage from DAC A. This is the buffer amplifier output voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and
±5 V. The amplifier is capable of developing
+10 V across a 2 k
resistor to GND.
23
VSS
Negative Supply (0 V or –12 V to –15 V).
24
ROFSA
Output Offset Resistor for DAC A. This input configures the output ranges for DAC A. It is connected to
VOUTA for the +5 V range, to AGND for the +10 V range and to REF INA for the
±5 V range.
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