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參數(shù)資料
| 型號： | AD7247ABRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT AMP/BUFF 24SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 1W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
AD7237A/AD7247A
REV. 0
–9–
Figure 6. AD7237A Input Control Logic
Table II. AD7237A Truth Table
CS WR
A1 A0 LDAC Function
1
X
X X 1
No Data Transfer
X
1
X X 1
No Data Transfer
0
1
DAC A LS Input Latch Transparent
0
1
DAC A MS Input Latch Transparent
0
1
0
1
DAC B LS Input Latch Transparent
0
1
DAC B MS Input Latch Transparent
1
X X 0
DAC A and DAC B DAC Latches
Updated Simultaneously from the
Respective Input Latches
X = Don’t Care.
However, care must be taken while exercising LDAC during a
write cycle. If an LDAC operation overlaps a CS and WR op-
eration, there is a possibility of invalid data being latched to the
output. To avoid this, LDAC must remain low after CS or WR
return high for a period equal to or greater than t8, the mini-
mum LDAC pulse width.
Figure 7. AD7237A Write Cycle Timing Diagram
Table I. AD7247A Truth Table
CSA
CSB
WR
Function
X
1
No Data Transfer
1
X
No Data Transfer
0
1
0
DAC A Latch Transparent
1
0
DAC B Latch Transparent
0
Both DAC Latches Transparent
X = Don’t Care
INTERFACE LOGIC INFORMATION—AD7237A
The input loading structure on the AD7237A is configured for
interfacing to microprocessors with an 8-bit-wide data bus. The
part contains two 12-bit latches per DAC—an input latch and a
DAC latch. Each input latch is further subdivided into a least
significant 8-bit latch and a most significant 4-bit latch. Only
the data held in the DAC latches determines the outputs from
the part. The input control logic for the AD7237A is shown in
Figure 6, while the write cycle timing diagram is shown in
Figure 7.
CS
, WR, A0 and A1 control the loading of data to the input
latches. The eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided
that LDAC is held high, there is no analog output change as a
result of loading data to the input latches. Address lines A0 and
A1 determine which latch data is loaded to when CS and WR
are low. The selection of the input latches is shown in the truth
table for AD7237A operation in Table II.
The LDAC input controls the transfer of 12-bit data from the
input latches to the DAC latches. Both DAC latches, and hence
both analog outputs, are updated at the same time. The LDAC
signal is level triggered, and data is latched into the DAC latch
on the rising edge of LDAC. The LDAC input is asynchronous
and independent of WR. This is useful in many applications
especially in the simultaneous updating of multiple AD7237As.
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