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參數(shù)資料
| 型號： | AD7248ABNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT W/REF 24DIP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 18 |
| 系列： | DACPORT® |
| 設置時間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 142k |
AD7245A/AD7248A
REV. B
–11–
BIPOLAR CONFIGURATION
The bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from –5 V to +5 V, is achieved by
connecting the ROFS input to REF OUT and connecting RFB
and VOUT. The AD7245A/AD7248A must be operated from
dual supplies to achieve this output voltage range. The code
table for bipolar operation is shown in Table IV.
Table IV. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output, VOUT
1 1 1 1
+VREF
×
2047
2048
1 0 0 0
0 0 0 0
0 0 0 1
+VREF
×
1
2048
1 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
–VREF
×
1
2048
0 0 0 0
0 0 0 1
–VREF
×
2047
2048
0 0 0 0
–VREF
×
2048
= –V
REF
NOTE:
1 LSB = 2
× V
REF(2
–11) = V
REF
1
2048
AGND BIAS
The AD7245A/AD7248A AGND pin can be biased above sys-
tem GND (AD7245A/AD7248A DGND) to provide an offset
“zero” analog output voltage level. With unity gain on the
amplifier (ROFS = VOUT = RFB) the output voltage, VOUT is
expressed as:
VOUT = VBIAS + D
VREF
where D is a fractional representation of the digital word in the
DAC latch and VBIAS is the voltage applied to the AD7245A/
AD7248A AGND pin.
Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped-
ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.
If a gain of 2 is used on the buffer amplifier the output voltage,
VOUT is expressed as
VOUT = 2(VBIAS + D
VREF)
In this case care must be taken to ensure that the maximum
output voltage is not greater than VDD –3 V. The VDD–VOUT
overhead must be greater than 3 V to ensure correct operation
of the part. Note that VDD and VSS for the AD7245A/AD7248A
must be referenced to DGND (system GND). The entire circuit
can be operated in single supply with the VSS pin of the
AD7245A/AD7248A connected to system GND.
REF
DAC
AD7245A/AD7248A*
15V
0.1 F
10
+
10 F
ROFS
VDD
2R
RFB
VOUT
VSS
DGND
AD589
27k
AGND
VBIAS
REF OUT
VREF
SYSTEM
GND
*DIGITAL CIRCUITRY
OMITTED FOR CLARITY.
+
–
Figure 9. AGND Bias Circuit
PROGRAMMABLE CURRENT SINK
Figure 10 shows how the AD7245A/AD7248A can be config-
ured with a power MOSFET transistor, the VN0300M, to
provide a programmable current sink from VDD or VSOURCE.
The VN0300M is placed in the feedback of the AD7245A/
AD7248A amplifier. The entire circuit can be operated in single
supply by tying the VSS of the AD7245A/AD7248A to AGND.
The sink current, ISINK, can be expressed as:
ISINK =
D
×V
REF
R1
REF
DAC
AD7245A/AD7248A*
0.1 F
10
+
10 F
ROFS
VDD
2R
RFB
VOUT
VSS
DGND
REF OUT
VREF
*DIGITAL CIRCUITRY
OMITTED FOR CLARITY.
AGND
VSOURCE
ISINK
LOAD
VN0300M
R1
Figure 10. Programmable Current Sink
Using the VN0300M, the voltage drop across the load can typi-
cally be as large as VSOURCE –6 V) with VOUT of the DAC at
5 V. Therefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200
with
VSOURCE = 15 V. The VN0300M can actually handle currents
up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of VSOURCE
otherwise it requires a very small load.
UNIPOLAR (0 V TO 5 V) CONFIGURATION
The 0 V to 5 V output voltage range is achieved by tying ROFS,
RFB and VOUT together. For this output range the AD7245A/
AD7248A can be operated single supply (VSS = 0 V) or dual sup-
ply. The table for output voltage versus digital code is as in Table
III, with 2
× V
REF replaced by VREF. Note that for this range
1 LSB = VREF(2
–12) = V
REF
1
4096
.
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