參數(shù)資料
型號(hào): AD7248ABRZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 8/16頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT W/REF 20-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,000
系列: DACPORT®
設(shè)置時(shí)間: 7µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
功率耗散(最大): 210mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 142k
AD7245A/AD7248A
REV. B
–16–
MECHANICAL INFORMATION —AD7248A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic DIP
(N-20)
20
110
11
PIN 1
1.07 (27.18) MAX
0.021 (0.533)
0.015 (0.381)
0.255 (6.477)
0.245 (6.223)
0.18 (4.57)
0.125 (3.18)
0.011 (0.28)
0.009 (0.23)
0.32 (8.128)
0.29 (7.366)
15
0
0.145
(3.683)
MIN
0.021 (0.533)
0.015 (0.381)
0.070 (1.77)
0.045 (1.15)
0.125
(3.175)
MIN
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
20-Lead SOIC
(R-20)
0.015 (0.38)
0.007 (0.18)
8
0
0.034 (0.86)
0.018 (0.46)
SEATING
PLANE
0.011 (0.275)
0.005 (0.125)
0.022 (0.56)
0.014 (0.36)
0.107 (2.72)
0.089 (2.26)
0.0500
(1.27)
BSC
20
11
10
1
0.419 (10.65)
0.404 (10.00)
0.299 (7.60)
0.291 (7.40)
PIN 1
0.5118 (13.00)
0.4961 (12.60)
20-Terminal
Plastic Leaded Chip Carrier
(P-20A)
3
PIN 1
IDENTIFIER
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.390
0.005
(9.905
0.125)
SQ
0.105
0.015
(2.665
0.375)
SQ
0.045
0.003
(1.143
0.076)
0.020
(0.51)
MAX
0.050
(1.27)
BSC
0.017
0.004
(0.432
0.101)
0.029
0.003
(0.737
0.076)
0.173
0.008
(4.385
0.185)
0.025
(0.64) MIN
0.020
(0.51) MIN
0.105
0.015
(2.665
0.375)
20-Lead Cerdip
(Q-20)
20
110
11
0.310 (7.87)
0.220 (5.59)
PIN 1
0.11 (2.79)
0.09 (2.28)
15°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.20 (5.0)
0.14 (3.18)
0.97 (24.64)
0.935 (23.75)
0.150
(3.81)
MIN
0.15 (3.8)
0.125 (3.18)
0.02 (0.5)
0.016 (0.41)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
C00996–0–3/01
(B)
PRINTED
IN
U.S.A.
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Changed VDD = 15 V
± 5% to VDD = 15 V ± 10% in Static Performance section in Test Conditions/Comments column . . . . . . . . 2
Changed A Version of Full-Scale Temperature Coefficient from
±30 to ±40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changed B and T Versions of VDD Power Requirements from +11.4/+15.75 to +10.8/+16.5 for V min.
Changed B and T Versions of VSS Power Requirements from –11.4/–15.75 to –10.8/–16.5 for V max . . . . . . . . . . . . . . . . . . . . . 2
Change to Note 1 and Note 9 of Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to Note 2 in Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to R-24 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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