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參數(shù)資料
| 型號： | AD724 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | RGB to NTSC/PAL Encoder(RGB-NTSC/PAL編碼器) |
| 中文描述： | RGB到的NTSC / PAL編碼器（RGB-NTSC/PAL編碼器） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 337K |
| 代理商： | AD724 |
a
RGB to NTSC/PAL Encoder
AD724
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1996
FEATURES
Low Cost, Integrated Solution
+5 V Operation
Accepts FSC Clock or Crystal, or 4FSC Clock
Composite Video and Separate Y/C (S-Video) Outputs
Luma and Chroma Outputs Are Time Aligned
Minimal External Components:
No External Filters or Delay Lines Required
Onboard DC Clamp
Accepts Either HSYNC & VSYNC or CSYNC
Phase Lock to External Subcarrier
Drives 75
V
Reverse-Terminated Loads
Logic Selectable NTSC or PAL Encoding Modes
Compact 16-Pin SOIC
APPLICATIONS
RGB to NTSC or PAL Encoding
PRODUCT DESCRIPTION
The AD724 is a low cost RGB to NTSC/PAL Encoder that
converts red, green and blue color component signals into their
corresponding luminance (baseband amplitude) and chromi-
nance (subcarrier amplitude and phase) signals in accordance
with either NTSC or PAL standards. These two outputs are
also combined to provide composite video output. All three out-
puts can simultaneously drive 75
, reverse-terminated cables.
All logical inputs are CMOS compatible. The chip operates
from a single +5 V supply. No external delay lines or filters are
required. The AD724 may be powered down when not in use.
The AD724 accepts either FSC or 4FSC clock. When a clock is
not available, a low cost parallel-resonant crystal (3.58 MHz
(NTSC) or 4.43 MHz (PAL)) and the AD724’s on-chip oscilla-
tor generate the necessary subcarrier clock. The AD724 also ac-
cepts the subcarrier clock from an external video source.
The interface to graphics controllers is simple: an on-chip logic
“XNOR” accepts the available vertical (VSYNC) and horizon-
tal sync (HSYNC) signals and creates the composite sync
(CSYNC) signal on-chip. If available, the AD724 will also ac-
cept a standard CSYNC signal by connecting VSYNC to +5 V
and applying CSYNC to the HSYNC pin. The AD724 contains
decoding logic to identify valid horizontal sync pulses for cor-
rect burst insertion.
Delays in the U and V chroma filters are matched by an on-chip
sampled-data delay line in the Y signal path. To prevent
aliasing, a prefilter at 5 MHz is included ahead of the delay line
and a post-filter at 5 MHz is added after the delay line to sup-
press harmonics in the output. These low-pass filters are opti-
mized for minimum pulse overshoot. The overall luma delay,
relative to chroma, has been designed to be time aligned for direct
input to a television’s baseband. The AD724 comes in a space-
saving SOIC and is specified for the 0
°
C to +70
°
C commercial
temperature range.
FUNCTIONAL BLOCK DIAGRAM
PHASE
DETECTOR
LOOP
FILTER
4FSC
4FSC
FSC
SUB-
CARRIER
NTSC/PAL
HSYNC
VSYNC
BURST
NTSC/PAL
FSC 90
°
FSC 0
°
4FSC
SC 90
°
/270
°
FSC
CSYNC
CSYNC
DC
CLAMP
RED
GREEN
BLUE
RGB-TO-YUV
ENCODING
MATRIX
CSYNC
Y
U
V
4-POLE
LPF
4-POLE
LPF
BALANCED
MODULATORS
4-POLE
LPF
NTSC/PAL
SAMPLED-
DATA
DELAY LINE
X2
X2
X2
LUMINANCE
OUTPUT
COMPOSITE
OUTPUT
CHROMINANCE
OUTPUT
U
CLAMP
CLOCK
AT 8FSC
4FSC
VCO
CHARGE
PUMP
XOSC
XNOR
SYNC
SEPARATOR
QUADRATURE
+4
DECODER
DC
CLAMP
DC
CLAMP
BURST
V
CLAMP
±
180
°
(PAL ONLY)
2-POLE
LP POST-
FILTER
3-POLE
LP PRE-
FILTER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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