參數(shù)資料
型號： AD7262BCPZ-5
廠商： Analog Devices Inc
文件頁數(shù)： 21/33頁
文件大?。?/td> 0K
描述： IC ADC 2CH 12BIT PGA/COM 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 120mW
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 管件
輸入數(shù)目和類型： 2 個差分，單極
AD7262
Rev. 0 | Page 27 of 32
The AD7262/AD7262-5 registers store the offset value that can
be accessed easily by the user (see the Reading from a Register
section). When the device is calibrating, the differential analog
inputs for each respective ADC are shorted together internally
and a conversion is performed. A digital code representing the
offset is stored internally in the offset registers, and subsequent
conversion results have this measured offset removed.
INTERNAL OFFSET CALIBRATION
The AD7262/AD7262-5 allow the user to calibrate the device
offset using the CAL pin. This is achieved by setting the CAL
pin to a high logic level, which initiates a calibration on the next
CS falling edge. The calibration requires one full conversion
cycle, which contains a CS falling edge followed by 19 SCLKs to
complete. The CAL pin can remain high for more than one
conversion if desired, and the AD7262/AD7262-5 continue to
calibrate.
When the AD7262/AD7262-5 are calibrated, the calibration
results stored in the internal device registers are only relevant
for the particular PGA gain selected at the time of calibration. If
the PGA gain is changed, the AD7262/AD7262-5 must be
recalibrated. If the device is not recalibrated when the PGA gain
is changed, the offset for the previous gain setting continues to
be removed from the digital output code, which may lead to
inaccuracies.
The CAL pin should only be driven high when the CS pin is high
or after 19 SCLK cycles have elapsed when CS is low (that is,
between conversions). The CAL pin must be driven high t12 ns
before CS goes low. If the CS pin goes low before the t12 has
elapsed, the calibration result is inaccurate for the current
conversion, but, provided that the CAL pin remains high, the
subsequent calibration conversion is correct. If the CAL pin is
set to a logic high state during a conversion, that conversion result
is corrupted.
The offset range, which can be calibrated for, is ±128 least
significant bits at a gain of 1. The maximum offset voltage,
which can be calibrated for, is reduced as the gain of the PGA
is increased.
Provided that the CAL pin has been held high for a minimum
of one conversion, and once t12 and t11 have been adhered to, the
calibration is complete after the 19th SCLK cycle, and the CAL
pin can be driven to a logic low state. The next CS falling edge
after the CAL pin has been driven to a low logic state initiates
a conversion of the differential analog input signal for both
ADC A and ADC B.
Table 12 details the maximum offset voltage, which can be
removed by the AD7262/AD7262-5 without compromising the
available digital output code range. The least significant bit size is
AVCC/2BITs, which is 5/4096 or 1.22 mV for the
AD7262/
AD7262-5. The maximum removable offset voltage is
given by
Gain
mV
22
.
1
LSB
128
×
±
Table 12. Offset Range
Alternatively, one can use the control register to initiate an
offset calibration. This is done by setting the CAL bit in the
control register to 1. The calibration is then initiated on the next
CS falling edge, but the current conversion is corrupted. The
ADCs on the AD7262/AD7262-5 must remain fully powered
up to complete the internal calibration.
Gain
Maximum Removable Offset Voltage
1
±156.16 mV
2
±78.08 mV
3
±52.053 mV
32
±4.88 mV1
1 This is the maximum removable offset for PGA gain ≥ 32.
CS
SCLK
CAL
20
12
3
21
19
t2
t6
t8
t7
t12
t11
31
30
21
20
19
3
2
1
07
60
6-
03
6
Figure 36. Calibration Timing Diagram
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