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參數(shù)資料
| 型號： | AD7266BSU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC |
| 中文描述： | DUAL 3-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQFP32 |
| 封裝： | MS-026ABA, TQFP-32 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大小： | 752K |
| 代理商： | AD7266BSU |
Preliminary Technical Data
AD7266
SERIAL INTERFACE
Figure 11 shows the detailed timing diagram for serial
interfacing to the AD7266. The serial clock provides the
conversion clock and controls the transfer of information from
the AD7266 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires a minimum of 14 SCLKs to complete. Once 13 SCLK
falling edges have elapsed, the track-and-hold will go back into
track on the next SCLK rising edge, as shown in Figure 11 at
point B. If a 16 SCK transfer is used then 2 trailing zeros will
appear after the final LSB. On the rising edge of CS, the
conversion will be terminated and D
OUT
A and D
OUT
B will go
back into three-state. If CS is not brought high but is instead
held low for a further 14 (or 16) SCLK cycles on D
OUT
A, the data
from conversion B will be output on D
OUT
A (followed by 2
trailing zeros). Likewise, if CS is held low for a further 14 (or 16)
SCLK cycles on D
OUT
B, the data from conversion A will be
output on D
OUT
B. This is illustrated in Figure 12 where the case
for D
OUT
A is shown. Note that in this case, the D
OUT
line in use
will go back into three-state on the 32nd SCLK falling edge or
the rising edge of CS, whichever occurs first
.
A minimum of fourteen serial clock cycles are required to
perform the conversion process and to access data from one
conversion on either data line of the AD7266. CS going low
provides the leading zero to be read in by the microcontroller or
DSP. The remaining data is then clocked out by subsequent
SCLK falling edges, beginning with a second leading zero. Thus
the first falling clock edge on the serial clock has the leading
zero provided and also clocks out the second leading zero. The
12 bit result then follows with the final bit in the data transfer
valid on the fourteenth falling edge, having being clocked out
on the previous (thirteenth) falling edge. In applications with a
slower SCLK, it may be possible to read in data on each SCLK
rising edge depending on the SCLK frequency used, i.e., the first
rising edge of SCLK after the CS falling edge would have the
leading zero provided and the thirteenth rising SCLK edge
would have DB0 provided.
SCLK
1
5
13
DOUTA
DOUTB
2 Leading Zeros
3-STATE
t
4
2
3
4
t
5
t
3
t
quiet
t
2
3-STATE
DB11
DB10
DB2
DB0
t
6
t
7
t
8
14
0
0
DB1
B
DB9
DB8
t
9
Figure 11 Serial Interface Timing Diagram
SCLK
1
5
t
5
15
DOUTA3-STATE
t
4
2
3
4
16
t
3
t
2
3-STATE
t
6
t
7
14
ZERO
0
ZERO
DB11B
17
2 Leading Zeros,
t
10
32
DB11A
2 Leading
Zeros,
DB10A
DB9A
ZERO
ZERO
ZERO
2 Traiing Zeros,
ZERO
ZERO
2 Traiing Zeros,
Figure 12. Reading data from Both ADCs on One D
OUT
Line with 32 SCLKs
Rev. PrG | Page 15 of 17
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