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參數(shù)資料
| 型號： | AD7273BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 243K |
| 代理商： | AD7273BRM |
–6–
REV. PrB
PRELIMINARY TECHNICAL DATA
AD7273/AD7274
TIMING SPECIFICATIONS
1
Preliminary Technical Data
Limit at T
MIN
, T
MAX
Parameter AD7273/AD7274 Units
Description
f
SCLK
2
20
52
14 x t
SCLK
12 x t
SCLK
KHz min
3
MHz max
AD7274
t
CONVERT
AD7273
t
QUIET
TBD
ns min
Minimum Quiet Time required between Bus Relinquish
and start of Next Conversion
Minimum
Pulse Width
to SCLK Setup Time
Delay from
Until SDATA Three-State Disabled
Data Access Time After SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power Up Time from Full Power-down
t
1
t
2
t
34
t
44
t
5
t
6
t
74
t
85
10
TBD
TBD
TBD
0.4t
SCLK
0.4t
SCLK
TBD
TBD
TBD
TBD
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
μ
s max
t
power-up6
NOTES
1
Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6Volts.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum
f
sclk
at which specifications are guaranteed.
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.
5
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
8
, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
6
See Power-up Time section.
Specifications subject to change without notice.
(
V
DD
= +2.35 V to +3.6 V; V
REF
= 2.5V
,
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Figure 1. Load Circuit for Digital Output
Timing Specifications
+1.6V
IOL
200μA
200μA
IOH
TO
OUTPUT
PIN
CL
25pF
VIH
VIL
t7
SCLK
SDATA
VIH
VIL
t4
SCLK
SDATA
1.6 V
t8
SCLK
SDATA
Figure 2. Access time after SCLK falling edge
Figure 3. Hold time after SCLK falling edge
Figure 4. SCLK falling edge to SDATA Three-State
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| AD7273BRMZ | 功能描述:IC ADC 10BIT 3MSPS HS LP 8MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7273BRMZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
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| AD7273BRMZ-REEL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| AD7273BUJ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:3MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
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