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參數(shù)資料
| 型號： | AD7276 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT |
| 中文描述： | 3MSPS，12/10/8位ADC的6引腳TSOT |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 255K |
| 代理商： | AD7276 |
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PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
AD7276/AD7277/AD7278
CIRCUIT INFORMATION
The AD7276/AD7277/AD7278 are fast, micropower, 12-/
10-/8-Bit, single supply, A/D converters respectively. The
parts can be operated from a +2.35V to +3.6V supply.
When operated from any supply voltage within this range,
the AD7276/AD7277/AD7278 are capable of throughput
rates of 3 MSPS when provided with a 52 MHz clock.
The AD7276/AD7277/AD7278 provide the user with an
on-chip track/hold, A/D converter, and a serial interface
housed in a tiny 6-lead TSOT or 8-lead MSOP package,
which offers the user considerable space saving advantages
over alternative solutions. The serial clock input accesses
data from the part but also provides the clock source for
the successive-approximation A/D converter. The analog
input range is 0 to V
DD
. An external reference is not
required for the ADC and neither is there a reference on-
chip. The reference for the AD7276/AD7277/AD7278 is
derived from the power supply and thus gives the widest
dynamic input range.
The AD7276/AD7277/AD7278 also feature a power down
option to allow power saving between conversions. The
Power-Down feature is implemented across the standard
serial interface as described in the Modes of Operation
section.
CONVERTER OPERATION
The AD7276/AD7277/AD7278 is a successive-
approximation analog-to-digital converter based around a
charge redistribution DAC. Figures 7 and 8 show
simplified schematics of the ADC. Figure 7 shows the
ADC during its acquisition phase. SW2 is closed and SW1
is in position A, the comparator is held in a balanced
condition and the sampling capacitor acquires the signal on
V
IN
.
When the ADC starts a conversion, see Figure 8, SW2
will open and SW1 will move to position B causing the
comparator to become unbalanced. The Control Logic
and the Charge Redistribution DAC are used to add and
subtract fixed amounts of charge from the sampling ca-
pacitor to bring the comparator back into a balanced con-
dition. When the comparator is rebalanced the conversion
is complete. The Control Logic generates the ADC out-
put code. Figure 9 shows the ADC transfer function.
Figure 7. ADC Acquisition Phase
CHARGE
REDISTRIBUTION
DAC
VIN
VDD / 2
SAMPLING
CAPACITOR
COMPARATOR
CONTROL
LOGIC
ACQUISITION
PHASE
SW1
A
B
SW2
AGND
ADC TRANSFER FUNCTION
The output coding of the AD7276/AD7277/AD7278 is
straight binary. The designed code transitions occur
midway between succesive integer LSB values, i.e,
0.5LSB, 1.5LSBs, etc. The LSB size is V
DD
/4096 for the
AD7276, V
DD
/1024 for the AD7277 and V
DD
/256 for the
AD7278. The ideal transfer characteristic for the AD7276/
AD7277/AD7278 is shown in Figure 9.
Figure 8. ADC Conversion Phase
CHARGE
REDISTRIBUTION
DAC
VIN
VDD / 2
SAMPLING
CAPACITOR
COMPARATOR
CONTROL
LOGIC
CONVERSION
PHASE
SW1
A
B
SW2
AGND
Figure 9. AD7276/AD7277/AD7278 Transfer Characteristic
000...000
0V
A
ANALOG INPUT
111...111
111...110
000...001
000...010
111...000
011...111
0.5LSB
+VDD-1.5LSB
1LSB = VDD/1024 (AD7277)
1LSB = VDD/256 (AD7278)
1LSB = VDD/4096 (AD7276)
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