參數(shù)資料
型號(hào)： AD7277BUJ-REEL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT
中文描述： 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6
封裝： MO-193AA, TSOT-6
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 255K
代理商： AD7277BUJ-REEL
–5–
REV. PrF
PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
TIMING SPECIFICATIONS
1
AD7276/AD7277/AD7278
Limit at T
MIN
, T
MAX
Parameter AD7276/AD7277/AD7278
Units
Description
f
SCLK
2
20
52
14 x t
SCLK
12 x t
SCLK
10 x t
SCLK
KHz min
3
MHz max
t
CONVERT
AD7276
AD7277
AD7278
t
QUIET
TBD
ns min
Minimum Quiet Time required between Bus Relinquish
and start of Next Conversion
Minimum
Pulse Width
to SCLK Setup Time
Delay from
Until SDATA Three-State Disabled
Data Access Time After SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power Up Time from Full Power-down
t
1
t
2
t
34
t
44
t
5
t
6
t
74
t
85
10
TBD
TBD
TBD
0.4t
SCLK
0.4t
SCLK
TBD
TBD
TBD
TBD
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
μ
s max
t
power-up6
NOTES
1
Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 Volts.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum
f
sclk
at which specifications are guaranteed.
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.
5
t
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
6
See Power-up Time section.
Specifications subject to change without notice.
(
V
DD
= +2.35 V to +3.6 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Figure 1. Load Circuit for Digital Output
Timing Specifications
+1.6V
IOL
200μA
200μA
IOH
TO
OUTPUT
PIN
CL
25pF
VIH
VIL
t7
SCLK
SDATA
VIH
VIL
t4
SCLK
SDATA
1.4 V
t8
SCLK
SDATA
Figure 2. Access time after SCLK falling edge
Figure 3. Hold time after SCLK falling edge
Figure 4. SCLK falling edge to SDATA Three-State
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