AD7276/AD7277/AD7278
Rev. C | Page 5 of 28
AD7277 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 1 MHz sine wave
Signal-to-Noise + Distortion (S
INAD)360.5
dB min
Total Harmonic Distortion (THD
)370
1
dB max
76
dB typ
Peak Harmonic or Spurious Noise
(SFDR)380
dB typ
Intermodulation Distortion
(IMD)3Second-Order Terms
82
dB typ
fa = 1 MHz, fb = 0.97 MHz
Third-Order Terms
82
dB typ
fa = 1 MHz, fb = 0.97 MHz
Aperture Delay
5
ns typ
Aperture Jitter
18
ps typ
Full Power Bandwidth
74
MHz typ
@ 3 dB
10
MHz typ
@ 0.1 dB
DC ACCURACY
Resolution
10
Bits
±0.5
LSB max
Differential Nonlinearit
y3±0.5
LSB max
Guaranteed no missed codes to 10 bits
±1.5
±1
LSB max
±2
±1.5
LSB max
Total Unadjusted Error (T
UE)3±2.5
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to VDD
V
DC Leakage Current
±1
μA max
40°C to +85°C
±5.5
μA max
85°C to 125°C
Input Capacitance
42
pF typ
When in track
10
pF typ
When in hold
LOGIC INPUTS
Input High Voltage, VINH
1.7
V min
2.35 V ≤ VDD ≤ 2.7 V
2
V min
2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VINL
0.7
V max
2.35 V ≤ VDD ≤ 2.7 V
0.8
V max
2.7 V < VDD ≤ 3.6 V
Input Current, IIN
±1
μA max
Typically 10 nA, VIN = 0 V or VDD
2
pF typ
LOGIC OUTPUTS
Output High Voltage, VOH
VDD 0.2
V min
ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V
Output Low Voltage, VOL
0.2
V max
ISINK = 200 μA
Floating-State Leakage Current
±2.5
μA max
Floating-State Output Capacitanc
e44.5
pF typ
Output Coding
Straight (natural) binary
CONVERSION RATE
Conversion Time
250
ns max
12 SCLK cycles with SCLK at 48 MHz
Track-and-Hold Acquisition Tim
e360
ns min
Throughput Rate
3.45
MSPS max
SCLK at 48 MHz