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參數資料
| 型號： | AD7291BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 28/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SAR 8CH 20-LFCSP |
| 標準包裝： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 22.22k |
| 數據接口： | I²C，串行 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 12.6mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 8 個單端，單極 |
| 配用： | EVAL-AD7291SDZ-ND - BOARD EVAL FOR AD7291 |
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Data Sheet
AD7291
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
3
4
SDA
15
SCL
AS1
ALERT
11
AS0
VIN3
VIN5
2
VIN4
VIN6
5
VIN7
7
V
R
E
F
6
G
N
D
1
8
D
C
A
P
9
G
N
D
1
0
V
D
1
9
V
IN
1
2
0
V
IN
2
1
8
V
IN
0
1
7
P
D
/R
S
T
1
6
V
D
R
IV
E
AD7291
TOP VIEW
(Not to Scale)
08
7
1
1-
0
03
NOTES
1. THE EXPOSED METAL PADDLE ON THE BOTTOM
OF THE LFCSP PACKAGE SHOULD BE SOLDERED
TO PCB GROUND FOR PROPER HEAT DISSIPATION
AND PERFORMANCE.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 5,
18 to 20
VIN3, VIN4,
VIN5, VIN6,
VIN7, VIN0,
VIN1, VIN2
Analog Inputs. The AD7291 has eight single-ended analog inputs that are multiplexed into the on-chip track-and-
hold amplifier. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should
be connected to GND1 to avoid noise pickup.
6
GND1
Ground. Ground reference point for the internal reference circuitry on the AD7291. All analog input signals and
the external reference signals should be referred to this GND1 voltage. The GND1 pin should be connected to the
ground plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis. The VREF pin should be decoupled to this ground pin via a 10 μF decoupling
capacitor.
7
VREF
Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin.
Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest
of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For best
performance, it is recommended to use a 10 μF decoupling capacitor on this pin to GND1. The internal reference
can be disabled and an external reference supplied to this pin if required. The input voltage range for the external
reference is 2.0 V to 2.5 V.
8
DCAP
Decoupling Capacitor Pin. Decoupling capacitors (1 μF recommended) are connected to this pin to decouple the
internal LDO.
9
GND
Ground. Ground reference point for all analog and digital circuitry on the AD7291. The GND pin should be con-
nected to the ground plane of the system. All ground pins should ideally be at the same potential and must not be
more than 0.3 V apart, even on a transient basis. Both DCAP and VDD pins should be decoupled to this GND pin.
10
VDD
Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 μF and 100 nF decoupling capacitors.
11, 13
AS0, AS1
Logic Input. Together, the logic state of these two inputs selects a unique I2C address for the AD7291. See Table 31
for details. The device address depends on the voltage applied to these pins.
12
ALERT
Digital Output. This pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion
result violates the DATAHIGH or DATALOW register values. See the Limit Registers (0x04 to 0x1E) section.
14
SDA
Digital Input/Output. Serial bus bidirectional data. This open-drain output requires a pull-up resistor. The output coding
is straight binary for the voltage channels and twos complement for the temperature sensor result.
15
SCL
Digital Input. Serial I2C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I2C mode is
compatible with both 100 kHz and 400 kHz operating modes.
16
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface operates.
This pin should be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and may be less than the
voltage at VDD but should never exceed it by more than 0.3 V.
17
PD/RST
Power-Down Pin. This pin places the part into a full power-down mode and enables power conservation when
operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a
maximum of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the device in
full power-down mode, the analog inputs must be returned to 0 V.
EPAD
Exposed Paddle. The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB
ground for proper functionality and heat dissipation.
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