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參數(shù)資料
| 型號(hào)： | AD7302BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 292K |
| 代理商： | AD7302BRU |
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AD7302
–10–
REV. 0
Automatic Update Mode
In this mode of operation the
LDAC
signal is permanently tied
low. The state of the
LDAC
is sampled on the rising edge of
WR
.
LDAC
being low allows the selected DAC register to be
automatically updated on the rising edge of
WR
. The output
update occurs on the rising edge of
WR
. Figure 23 shows the
timing associated with the automatic update mode of operation
and also the status of the various registers during this frame.
A
/B
CS
WR
D7–D0
LDAC
= 0
HOLD
HOLD
TRACK
I/P REG (MLE)
TRACK
HOLD
DAC REG (SLE)
TRACK
V
OUT
Figure 23. Timing and Register Arrangement for Auto-
matic Update Mode
Simultaneous Update Mode
In this mode of operation the
LDAC
signal is used to update both
DAC outputs simultaneously. The state of the
LDAC
is sampled
on the rising edge of
WR
. If
LDAC
is high, the automatic update
mode is disabled and both DAC latches are updated at any time
after the write by taking
LDAC
low. The output update occurs
on the falling edge of
LDAC
.
LDAC
must be taken back high
again before the next data transfer takes place. Figure 24
shows the timing associated with the simultaneous update mode
of operation and also the status of the various registers during
this frame.
A
/B
CS
WR
D7–D0
LDAC
HOLD
HOLD
TRACK
I/P REG (MLE)
TRACK
HOLD
DAC REG (SLE)
V
OUT
HOLD
Figure 24. Timing and Register Arrangement for Simulta-
neous Update Mode
POWER-ON RESET
The AD7302 has a power-on reset circuit designed to allow
output stability during power-up. This circuit holds the DACs
in a reset state until a write takes place to the DAC. In the reset
state all zeros are latched into the input registers of each DAC
and the DAC registers are in transparent mode, thus the output
of both DACs is held at ground potential until a write takes
place to the DAC. The power-on reset circuitry generates a
PON STRB signal, which is a gating signal used within the logic
to identify a power-on condition.
POWER-DOWN FEATURES
The AD7302 has a power-down feature. This is implemented
by exercising the external
PD
pin; an active low signal puts the
complete DAC into power-down mode. When in power-down
the current consumption of the device is reduced to 1
μ
A max at
25
°
C and 2
μ
A max over temperature, making the device
suitable for use in portable battery powered equipment. When
power-down is activated, the reference bias servo loop and the
output amplifiers with their associated linear circuitry are
powered down, the reference resistors are open circuited to
further reduce the power consumption. The output sees a load
of approximately 23 k
to GND when in power-down mode as
shown in Figure 25. The contents of the data registers are
unaffected when in power-down mode. The device comes out
of power-down in typically 13
μ
s (see Figure 10).
I
DAC
11.7k
11.7k
V
REF
V
DD
Figure 25. Output Stage During Power-Down
Analog Outputs
The AD7302 contains two independent voltage output DACs
with 8-bit resolution and rail-to-rail operation. The output buffer
provides a gain of two at the output. Figures 2 to 4 show the
source and sink capabilities of the output amplifier. The slew
rate of the output amplifier is typically 7.5 V/
μ
s and has a full-
scale settling to 8 bits with a 100 pF capacitive load in typically
1.2
μ
s.
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7302. Figure 26 shows
the DAC transfer function for binary coding. Any DAC output
voltage can be expressed as:
V
OUT
= 2
×
V
REF
(
N
/256)
where:
N
is the decimal equivalent of the binary input code.
N
ranges from 0 to 255.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7302 | Parallel Input Dual Voltage Output 8-Bit DAC(串行輸入,電壓輸出雙8位D/A轉(zhuǎn)換器) |
| AD7303 | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7303BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7303BR | +2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC |
| AD7303BRM | +2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7302BRU-REEL | 制造商:Analog Devices 功能描述:DAC 2-CH 8-bit 20-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH 8BIT 20TSSOP - Tape and Reel |
| AD7302BRU-REEL7 | 制造商:Analog Devices 功能描述:DAC 2-CH 8-bit 20-Pin TSSOP T/R |
| AD7302BRUZ | 功能描述:IC DAC 8BIT DUAL R-R 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD7302BRUZ | 制造商:Analog Devices 功能描述:IC 8-BIT DAC |
| AD7302BRUZ-REEL | 功能描述:IC DAC 8BIT DUAL R-R 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 設(shè)計(jì)資源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 標(biāo)準(zhǔn)包裝:10,000 系列:- 設(shè)置時(shí)間:- 位數(shù):12 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 薄型，TSOT-23-8 供應(yīng)商設(shè)備封裝:TSOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:2.7M |
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