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參數(shù)資料
| 型號： | AD7303BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封裝： | MICRO, SOIC-8 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 361K |
| 代理商： | AD7303BRM |
AD7303
–13–
REV. 0
SCLK
V
DD
10k
AD7303
DIN
SYNC
SCLK
V
DD
REF
POWER
+5V
REGULATOR
V
OUT
B
V
OUT
A
AGND
10μF
0.1μF
0.1μF
V
DD
10k
DATA
V
DD
10k
SYNC
Figure 32. AD7303 in Opto-Isolated Interface
Decoding Multiple AD7303
The
SYNC
pin on the AD7303 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same serial clock and serial data, but only the
SYNC
to one of the DACs will be active at any one time allow-
ing access to two channels in this eight-channel system. The
74HC139 is used as a 2- to 4-line decoder to address any of the
DACs in the system. To prevent timing errors from occurring,
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 33 shows a dia-
gram of a typical setup for decoding multiple AD7303 devices in
a system.
ENABLE
74HC139
AD7303
SYNC
DIN
SCLK
DIN
SCLK
DGND
CODED
ADDRESS
1A
1B
1Y0
1Y1
1Y2
1Y3
V
CC
V
DD
1
G
AD7303
SYNC
DIN
SCLK
AD7303
SYNC
DIN
SCLK
AD7303
SYNC
DIN
SCLK
Figure 33. Decoding Multiple AD7303 Devices in a System
AD7303 as a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD7303 is shown in Figure 34. The upper
and lower limits for the test are loaded to DACs A and B which,
in turn, set the limits on the CMP04. If a signal at the V
IN
input
is not within the programmed window, a led will indicate the fail
condition.
AD7303
V
DD
+5V
V
OUT
A
GND
0.1μF
REF
V
IN
PASS/
FAIL
1/2
CMP04
1/6 74HC05
FAIL
PASS
1k
0.1μF
10μF
SCLK
DIN
SYNC
SCLK
DIN
SYNC
1k
V
OUT
B
Figure 34. Window Detector Using AD7303
Programmable Current Source
Figure 35 shows the AD7303 used as the control element of a
programmable current source. In this circuit, the full-scale cur-
rent is set to 1 mA. The output voltage from the DAC is applied
across the current setting resistor of 4.7 k
in series with the
full-scale setting resistor of 470
. Suitable transistors to place
in the feedback loop of the amplifier include the BC107 and the
2N3904, which enable the current source to operate from a min
V
SOURCE
of 6 V. The operating range is determined by the oper-
ating characteristics of the transistor. Suitable amplifiers in-
clude the AD820 and the OP295, both having rail-to-rail
operation on their outputs. The current for any digital input
code can be calculated as follows:
I
= 2
×
V
REF
×
D
/(5
E
+ 3
×
256) mA
4.7k
470
+5V
LOAD
V
SOURCE
AD7303
V
OUT
A
10μF
0.1μF
V
DD
= +5V
V
DD
GND
AD780/ REF192
WITH V
DD
= +5V
REF
SCLK
DIN
SYNC
GND
V
OUT
V
IN
0.1μF
SERIAL
INTERFACE
EXT
REF
AD820/
OP295
Figure 35. Programmable Current Source
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