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| 型號： | AD7304 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | 3伏/ 5伏，軌至軌四路，8位DAC |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 936K |
| 代理商： | AD7304 |
AD7304/AD7305
–
12
–
REV. A
AD7304
RINPUT
R
DAC A
OE
RDAC A
R
RINPUT
R
DAC B
OE
RDAC C
R
RDAC B
R
RINPUT
R
DAC C
OE
RDAC D
R
DACA
B
C
D
2:4
A0
A1
SDC
SAC
D0
D1
D2
D3
D4
D5
D6
D7
8
EN
320k
280k
80k
640k
680k
V
DD
LDAC
V
SS
V
OUT
C
CS
CLK
SDI
V
OUT
B
V
OUT
A
V
DD
D Q
g
D Q
g
D Q
g
D Q
g
RINPUT
R
POWER-
RON
V
REF
A
V
REF
B
V
REF
C
V
REF
D
V
OUT
D
CLR
GND
DAC D
OE
Figure 31. AD7304 Equivalent Logic Interface
AD7304 Hardware Shutdown SHDN
If a three-state driver is used on the SDI/SHDN pin, the AD7304
can be placed into a power shutdown mode when the SDI/
SHDN pin is placed in a high impedance state. For proper
operation no other termination voltages should be present on
this pin. An internal window comparator will detect when the
logic voltage on the SHDN pin is between 28% and 36% of
V
DD
. A high impedance internal bias generator provides this
voltage on the SHDN pin. The four DAC output voltages be-
come high impedance with a nominal resistance of 120 k
to
ground. See Figure 30 for an equivalent circuit.
AD7304/AD7305 POWER ON RESET
When the V
DD
power supply is turned on, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state. The V
DD
power supply should have a monotonically in-
creasing ramp in order to have consistent results, especially in
the region of V
DD
= 1.5 V to 2.3 V. The V
SS
supply has no effect
on the power ON reset performance. The DAC register data
will stay at zero until a valid serial register software load takes
place. In the case of the double buffered AD7305 the output
DAC register can only be changed once the
LDAC
strobe is
initiated.
AD7305 PARALLEL DATA INTERFACE
The AD7305 has an 8-bit parallel interface DB7 = MSB,
DB0 = LSB. Two address Bits A1 and A0 are decoded when an
active low write strobe is placed on the
WR
pin, see Table III.
The
WR
is a level-sensitive input pin, therefore the data setup
and data hold times defined in the TIMING SPECIFICATIONS
need to be adhered to.
The
LDAC
pin provides the capability of simultaneously updat-
ing all DAC registers with new data from the Input Registers at
the same time. This will result in the analog outputs all chang-
ing to their new values at the same time. The
LDAC
pin is a
level-sensitive input. If the simultaneous update feature is not
required the
LDAC
pin can be tied to logic low. When the
LDAC
is tied to logic low, the DAC Registers become transpar-
ent and the Input Register data determines the DAC output
voltage. See Figure 32 for an equivalent interface logic diagram.
AD7226 Pin Compatibility
By tying the
LDAC
pin to ground, the AD7305 has the same
pin out and functionality as the AD7226, with the exception of
a lower power supply operating voltage.
AD7305 Hardware Shutdown SHDN
If a three state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation no
other termination voltages should be present on this pin. An
internal window comparator will detect when the logic voltage
on the SHDN pin is between 28% and 36% of V
DD
. A high
impedance internal bias generator provides this voltage on the
SHDN pin. The four DAC output voltages become high imped-
ance with a nominal resistance of 120 k
to ground.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The V
REF
pins also contain a
back-biased ESD protection Zener connected to V
DD
(see
Figure 33).
GND
DIGITAL
INPUTS
V
DD
V
REF
X
Figure 33. Equivalent ESD Protection Circuits
AD7305
RINPUT
R
DAC A
OE
RDAC A
R
RINPUT
R
DAC B
OE
RDAC C
R
RDAC B
R
RINPUT
R
DAC C
OE
RDAC D
R
DAC A
B
C
D
2:4
8
320k
280k
80k
640k
680k
V
DD
LDAC
V
SS
V
OUT
C
WR
V
OUT
B
V
OUT
A
V
DD
RINPUT
R
POWER-
RON
V
REF
V
OUT
D
GND
DATA
DB0
–
DB7
DAC D
OE
A1
A0/SHDN
Figure 32. AD7305 Equivalent Logic Interface
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| AD7305 | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
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