參數(shù)資料
型號(hào)： AD7304BN
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
中文描述： SERIAL INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, PDIP16
封裝： PLASTIC, DIP-16
文件頁(yè)數(shù)： 11/14頁(yè)
文件大?。?/td> 936K
代理商： AD7304BN
–
11
–
AD7304/AD7305
REV. A
CIRCUIT OPERATION
The AD7304/AD7305 are a set of four-channel, 8-bit, voltage-
output, digital-to-analog converters differing primarily in digital
logic interface and number of reference inputs. Both parts share
the same internal DAC design and true rail-to-rail output buff-
ers. The AD7304 contains four independent multiplying refer-
ence inputs, while the AD7305 has one common reference input.
The AD7304 uses a 3-wire SPI compatible serial data interface,
while the AD7305 offers a 8-bit parallel data interface.
D/A Converter Section
Each part contains four voltage-switched R-2R ladder DACs.
Figure A shows a typical equivalent DAC. These DACs are
designed to operate both single-supply or dual supply, depend-
ing on whether the user supplies a negative voltage on the V
SS
pin. In a single-supply application the V
SS
is tied to ground. In
either mode the DAC output voltage is determined by the V
REF
input voltage and the digital data (D) loaded into the corre-
sponding DAC register according to Equation 1.
V
OUT
=
V
REF
×
D
/256
Note that the output full-scale polarity is the same as the V
REF
polarity for dc reference voltages.
(1)
V
REF
DB72R
V
DD
V
SS
V
OUT
R
2R
DB62R
DB02R
Figure 29. Typical Equivalent DAC Channel
These DACs are also designed to accommodate ac reference
input signals. As long as the ac signals are maintained between
V
SS
< V
REF
<V
DD
, the user can expect 50 kHz of full-power
multiplying bandwidth performance. In order to use negative
input reference voltages, the V
SS
pin must be biased with a nega-
tive voltage of equal or greater magnitude than the reference
voltage.
The reference inputs are code-dependent, exhibiting worst case
minimum resistance values specified in the parametric specifica-
tion table. The DAC outputs V
OUT
A, B, C, D are each capable
of driving 2 k
loads in parallel with up to 500 pF loads. Output
source and sink current is shown in Figures 6 and 7. The output
slew rate is nominally 3.6 V/
μ
s while operating from
±
5 V sup-
plies. The low output impedance of the buffers minimizes
crosstalk between analog input channels. At 100 kHz, 65 dB of
channel-to-channel isolation exists (Figure 22). Output voltage
noise is plotted in Figure 19. In order to maintain good analog
performance, power supply bypassing of 0.01
μ
F in parallel with
1
μ
F is recommended. The true rail-to-rail capability of the
AD7304/AD7305 allows the user to connect the reference inputs
directly to the same supply as the V
DD
or V
SS
pin (Figure 30).
Under these conditions clean power supply voltages (low ripple,
avoid switching supplies) appropriate for the application should
be used.
V
DD
V
SS
V
OUT
X
120k
Q1
Q2
Figure 30. Equivalent DAC Amplifier Output Circuit
AD7304 SERIAL DATA INTERFACE
The AD7304 uses a 3-wire (
CS
, SDI, CLK) SPI compatible
serial data interface. New serial data is clocked into the serial
input register in a 12-bit data-word format. MSB bits are loaded
first. Table II defines the 12 data-word bits. Data is placed on
the SDI/SHDN pin and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the TIMING SPECIFICATIONS.
Data can only be clocked in while the
CS
chip select pin is
active low. Only the last 12-bits clocked into the serial register
will be interrogated when the
CS
pin returns to the logic high
state, extra data bits are ignored. Since most microcontrollers
output serial data in 8-bit bytes, two right justified data bytes
can be written to the AD7304. Keeping the
CS
line low between
the first and second byte transfer will result in a successful serial
register update.
Once the data is properly aligned in the shift register the positive
edge of the
CS
initiates either the transfer of new data to the
target DAC register, determined by the decoding of address bits
A1 and A0, or the shutdown features will be activated based on
the SAC or SDC bits. When either SAC or SDC pins are set
(Logic = 0) the loading of new data determined by Bits B9 to
B0 are still loaded, but the results do not appear on the buffer
outputs until the device is brought out of the shutdown state.
The selected DAC output voltages become high impedance with
a nominal resistance of 120 k
to ground, Figure 30. If both
SAC and SDC pins are set, all channels are still placed in the
shutdown mode. When the AD7304 has been programmed into
the power shutdown state, the present DAC register data is
maintained as long as V
DD
remains greater than 2.7 volts. The
remaining characteristics of the software serial interface are
defined by Tables I, II and Figure 3 timing diagram.
Two additional pins
CLR
and
LDAC
on the AD7304 provide
hardware control over the clear function and the DAC Register
loading. If these functions are not needed the
CLR
pin can be
tied to logic high, and the
LDAC
pin can be tied to logic low.
The asynchronous input
CLR
pin forces all input and DAC
registers to the zero-code state. The asynchronous
LDAC
pin
can be strobed to active low when all DAC Registers need to be
updated simultaneously from their respective Input Registers.
The
LDAC
pin places the DAC Register in a transparent mode
while in the logic low state.
相關(guān)PDF資料
PDF描述
AD7304BR +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC
AD7304BRU +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC
AD7304YR ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75%
AD7305 ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
AD7305BN +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AD7304BR 功能描述:IC DAC 8BIT QUAD R-R 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:*
AD7304BR-REEL 功能描述:IC DAC 8BIT QUAD R-R 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:*
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AD7304BRU REEL 制造商:Analog Devices 功能描述:
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