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參數(shù)資料
| 型號： | AD7304BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD R-R 16TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 1µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 60mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 1M |
AD7304/AD7305
Rev. C | Page 9 of 20
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VOUTA
VSS
VREF
DB7
LDAC
GND
VOUTB
VOUTD
VDD
A0/SHDN
DB0
WR
A1
DB4
DB5
DB6
DB3
DB2
DB1
VOUTC
AD7305
TOP VIEW
(Not to Scale)
01114-009
Figure 9. AD7305 Pin Configuration
Table 8. AD7305 Pin Function Description
Pin No.
Mnemonic
Description
1
VOUTB
Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin. Output is
open circuit when SHDN is enabled.
2
VOUTA
Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin. Output is
open circuit when SHDN is enabled.
3
VSS
Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V.
4
VREF
Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation is VSS < VREF < VDD.
5
GND
Common Analog and Digital Ground.
6
LDAC
Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the
corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 6
for operation.
7
DB7
MSB Digital Input Data Bit.
8
DB6
Data Bit 6.
9
DB5
Data Bit 5.
10
DB4
Data Bit 4.
11
DB3
Data Bit 3.
12
DB2
Data Bit 2.
13
DB1
Data Bit 1.
14
DB0
LSB Digital Input Data Bit.
15
WR
Write Data into Input Register Control Line, Active Low. See Table 6 for operation.
16
A1
Address Bit 1.
17
A0/SHDN
Address Bit 0/Hardware Shutdown (SHDN) Control Input, Active When Pin Is Left Floating by a Three-State Logic
Driver. Does not effect DAC register contents as long as power is present on VDD.
18
VDD
Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.
19
VOUTD
Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin. Output is
open circuit when SHDN is enabled.
20
VOUTC
Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin. Output is
open circuit when SHDN is enabled.
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| AD7304BRZ | 功能描述:IC DAC 8BIT QUAD R-R 16-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD7304BRZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, Rail-to-Rail Quad, 8-Bit DAC |
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